diff options
author | Andrew Waterman <andrew@sifive.com> | 2019-07-11 13:54:53 -0700 |
---|---|---|
committer | Andrew Waterman <andrew@sifive.com> | 2019-07-11 13:54:53 -0700 |
commit | 44d497f1d8660c404449157a3fe126183cda7966 (patch) | |
tree | 6d0d39cbd47b56e1c676a3489fde6c0942d66ad5 /ChangeLog.md | |
parent | 0898d20da669a01f87ff203fa47b5dc53ed1d157 (diff) | |
download | riscv-isa-sim-44d497f1d8660c404449157a3fe126183cda7966.zip riscv-isa-sim-44d497f1d8660c404449157a3fe126183cda7966.tar.gz riscv-isa-sim-44d497f1d8660c404449157a3fe126183cda7966.tar.bz2 |
ChangeLog formatting
Diffstat (limited to 'ChangeLog.md')
-rw-r--r-- | ChangeLog.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ChangeLog.md b/ChangeLog.md index 6407a00..2dedbd3 100644 --- a/ChangeLog.md +++ b/ChangeLog.md @@ -1,7 +1,7 @@ Version 1.0.1-dev ----------------- - Preliminary support for a subset of the Vector Extension, v0.7.1. -- Support S-mode vectored interrupts (i.e. stvec[0] is now writable). +- Support S-mode vectored interrupts (i.e. `stvec[0]` is now writable). - Several debug-related additions and changes: - Added `hasel` debug feature. - Added `--dm-no-abstract-csr` command-line option. |