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| author | Andrew Waterman <andrew@sifive.com> | 2023-04-04 13:10:34 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-04-04 13:10:34 -0700 |
| commit | eb75ab37a17ff4f8597b7b40283a08c38d2a6ff6 (patch) | |
| tree | 9ef282c2bd8f18a4a124134a948aba07b23543a5 | |
| parent | 7f4c6eb4693b3726fc856de99811c55e94e8b837 (diff) | |
| parent | 96c64bce53ea3d8fa0344498b5512e5e2afd22bb (diff) | |
| download | riscv-isa-sim-eb75ab37a17ff4f8597b7b40283a08c38d2a6ff6.zip riscv-isa-sim-eb75ab37a17ff4f8597b7b40283a08c38d2a6ff6.tar.gz riscv-isa-sim-eb75ab37a17ff4f8597b7b40283a08c38d2a6ff6.tar.bz2 | |
Merge pull request #1307 from Jakub-Palider/master-stats-always
Print cache stats even when no access
| -rw-r--r-- | riscv/cachesim.cc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/riscv/cachesim.cc b/riscv/cachesim.cc index 498d407..24e87d3 100644 --- a/riscv/cachesim.cc +++ b/riscv/cachesim.cc @@ -76,9 +76,6 @@ cache_sim_t::~cache_sim_t() void cache_sim_t::print_stats() { - if (read_accesses + write_accesses == 0) - return; - float mr = 100.0f*(read_misses+write_misses)/(read_accesses+write_accesses); std::cout << std::setprecision(3) << std::fixed; |