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| author | Andrew Waterman <andrew@sifive.com> | 2019-07-19 00:51:37 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-07-19 00:51:37 -0700 |
| commit | de967334ef8d7044f4de5ff521398342127404e7 (patch) | |
| tree | 6e7d2368689902eacecd9cea76f552f3a709f639 | |
| parent | 4ae4845f234e9f2e06e9849b14cd5bc337efcead (diff) | |
| download | riscv-isa-sim-de967334ef8d7044f4de5ff521398342127404e7.zip riscv-isa-sim-de967334ef8d7044f4de5ff521398342127404e7.tar.gz riscv-isa-sim-de967334ef8d7044f4de5ff521398342127404e7.tar.bz2 | |
VL and VTYPE aren't writable CSRs
| -rw-r--r-- | riscv/processor.cc | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index c109342..37e0d60 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -665,18 +665,6 @@ void processor_t::set_csr(int which, reg_t val) case CSR_VXRM: VU.vxrm = val; break; - case CSR_VL: - VU.vl = val; - break; - case CSR_VTYPE: - VU.vtype = val; - // check vill bit - if (BITS(VU.vtype, get_xlen(), get_xlen() - 1) == 1){ - VU.vill = true; - }else{ - VU.vill = false; - } - break; } } |