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author | Atul Khare <atulkhare@rivosinc.com> | 2023-05-16 15:11:44 -0700 |
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committer | Atul Khare <atulkhare@rivosinc.com> | 2023-05-24 09:15:27 -0700 |
commit | d9e30bb6970c3e387d719b3fd0808937889ca3a6 (patch) | |
tree | f4734165397f34106df5c02fc95bcbd5b56f4c56 | |
parent | 31f5ede662303183d93f80e869379e49b7a01608 (diff) | |
download | riscv-isa-sim-d9e30bb6970c3e387d719b3fd0808937889ca3a6.zip riscv-isa-sim-d9e30bb6970c3e387d719b3fd0808937889ca3a6.tar.gz riscv-isa-sim-d9e30bb6970c3e387d719b3fd0808937889ca3a6.tar.bz2 |
triggers: Fix etrigger match on exceptions
The etrigger match on exceptions doesn't work properly in cases like
the following:
1) M-mode delegates ECALLs to S-mode
2) A CPU hardware point mechanism is used to place a breakpoint on the
Umode instruction that executes the ECALL from Umode to Smode. In
effect, this creates a breakpoint etrigger based on Umode.
In the above, the expectation is that #2 will first cause an exit to
the Smode handler (stvec), and the hardware breakpoint exception will
be triggered following an entry into the handler.
However, since etrigger currently checks the current privilege mode, we
will never get a match on conditions like #2.
The patch attempts to address the issue by using the stashed version of
the previous privilege mode for the etrigger match.
cc: YenHaoChen <howard25336284@gmail.com>
Signed-off-by: Atul Khare <atulkhare@rivosinc.com>
-rw-r--r-- | riscv/triggers.cc | 9 | ||||
-rw-r--r-- | riscv/triggers.h | 2 |
2 files changed, 7 insertions, 4 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 51dcf18..65ba4c9 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -55,9 +55,11 @@ void trigger_t::tdata3_write(processor_t * const proc, const reg_t val) noexcept sselect = (sselect_t)((proc->extension_enabled_const('S') && get_field(val, CSR_TEXTRA_SSELECT(xlen)) <= SSELECT_MAXVAL) ? get_field(val, CSR_TEXTRA_SSELECT(xlen)) : SSELECT_IGNORE); } -bool trigger_t::common_match(processor_t * const proc) const noexcept { +bool trigger_t::common_match(processor_t * const proc, bool use_prev_prv) const noexcept { auto state = proc->get_state(); - return mode_match(state->prv, state->v) && textra_match(proc); + auto prv = use_prev_prv ? state->prev_prv : state->prv; + auto v = use_prev_prv ? state->prev_v : state->v; + return mode_match(prv, v) && textra_match(proc); } bool trigger_t::mode_match(reg_t prv, bool v) const noexcept @@ -398,7 +400,8 @@ void itrigger_t::tdata1_write(processor_t * const proc, const reg_t val, const b std::optional<match_result_t> trap_common_t::detect_trap_match(processor_t * const proc, const trap_t& t) noexcept { - if (!common_match(proc)) + // Use the previous privilege for matching + if (!common_match(proc, true)) return std::nullopt; auto xlen = proc->get_xlen(); diff --git a/riscv/triggers.h b/riscv/triggers.h index 94e7e5c..0bf6097 100644 --- a/riscv/triggers.h +++ b/riscv/triggers.h @@ -90,7 +90,7 @@ public: protected: static action_t legalize_action(reg_t val, reg_t action_mask, reg_t dmode_mask) noexcept; - bool common_match(processor_t * const proc) const noexcept; + bool common_match(processor_t * const proc, bool use_prev_prv = false) const noexcept; bool allow_action(const state_t * const state) const; reg_t tdata2; |