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author | Ved Shanbhogue <ved@rivosinc.com> | 2024-05-04 15:30:10 -0500 |
---|---|---|
committer | Ved Shanbhogue <ved@rivosinc.com> | 2024-05-06 18:21:06 -0500 |
commit | c5229c3f5f4b6404977bb4134f1a0bda5207ff90 (patch) | |
tree | fd9c817dd725bd138d80782915b59379b809780f | |
parent | 7438d1e69286470b7aaa0a713fd853fdf5c12416 (diff) | |
download | riscv-isa-sim-c5229c3f5f4b6404977bb4134f1a0bda5207ff90.zip riscv-isa-sim-c5229c3f5f4b6404977bb4134f1a0bda5207ff90.tar.gz riscv-isa-sim-c5229c3f5f4b6404977bb4134f1a0bda5207ff90.tar.bz2 |
Add Zawrs extension
-rw-r--r-- | disasm/disasm.cc | 5 | ||||
-rw-r--r-- | disasm/isa_parser.cc | 10 | ||||
-rw-r--r-- | riscv/insns/wrs_nto.h | 6 | ||||
-rw-r--r-- | riscv/insns/wrs_sto.h | 1 | ||||
-rw-r--r-- | riscv/isa_parser.h | 1 | ||||
-rw-r--r-- | riscv/riscv.mk.in | 5 |
6 files changed, 26 insertions, 2 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index 6716e5b..7c07ec3 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -880,6 +880,11 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) DEFINE_XAMO(amocas_h) } + if (isa->extension_enabled(EXT_ZAWRS)) { + DEFINE_NOARG(wrs_sto); + DEFINE_NOARG(wrs_nto); + } + if (isa->extension_enabled(EXT_ZICFILP)) { // lpad encodes as `auipc x0, label`, so it needs to be added before auipc // for higher disassembling priority diff --git a/disasm/isa_parser.cc b/disasm/isa_parser.cc index c0869f3..ee57a51 100644 --- a/disasm/isa_parser.cc +++ b/disasm/isa_parser.cc @@ -123,6 +123,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv) extension_table[EXT_ZACAS] = true; } else if (ext_str == "zabha") { extension_table[EXT_ZABHA] = true; + } else if (ext_str == "zawrs") { + extension_table[EXT_ZAWRS] = true; } else if (ext_str == "zmmul") { extension_table[EXT_ZMMUL] = true; } else if (ext_str == "zba") { @@ -378,14 +380,18 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv) bad_isa_string(str, "'Zcf/Zcd/Zcb/Zcmp/Zcmt' extensions require 'Zca' extension"); } - if (extension_table[EXT_ZACAS] && !extension_table['A'] && !extension_table[EXT_ZAAMO]) { + if (extension_table[EXT_ZACAS] && !extension_table[EXT_ZAAMO]) { bad_isa_string(str, "'Zacas' extension requires either the 'A' or the 'Zaamo' extension"); } - if (extension_table[EXT_ZABHA] && !extension_table['A'] && !extension_table[EXT_ZAAMO]) { + if (extension_table[EXT_ZABHA] && !extension_table[EXT_ZAAMO]) { bad_isa_string(str, "'Zabha' extension requires either the 'A' or the 'Zaamo' extension"); } + if (extension_table[EXT_ZAWRS] && !extension_table[EXT_ZALRSC]) { + bad_isa_string(str, "'Zabha' extension requires either the 'A' or the 'Zalrsc' extension"); + } + // When SSE is 0, Zicfiss behavior is defined by Zicmop if (extension_table[EXT_ZICFISS] && !extension_table[EXT_ZIMOP]) { bad_isa_string(str, "'Zicfiss' extension requires 'Zimop' extension"); diff --git a/riscv/insns/wrs_nto.h b/riscv/insns/wrs_nto.h new file mode 100644 index 0000000..710e670 --- /dev/null +++ b/riscv/insns/wrs_nto.h @@ -0,0 +1,6 @@ +if (get_field(STATE.mstatus->read(), MSTATUS_TW)) { + require_privilege(PRV_M); +} else if (STATE.v) { + if (get_field(STATE.hstatus->read(), HSTATUS_VTW)) + require_novirt(); +} diff --git a/riscv/insns/wrs_sto.h b/riscv/insns/wrs_sto.h new file mode 100644 index 0000000..4e71aa0 --- /dev/null +++ b/riscv/insns/wrs_sto.h @@ -0,0 +1 @@ +// WRS.STO stalls for a short duration diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h index 4bd9d4b..65c34fd 100644 --- a/riscv/isa_parser.h +++ b/riscv/isa_parser.h @@ -68,6 +68,7 @@ typedef enum { EXT_ZALRSC, EXT_ZACAS, EXT_ZABHA, + EXT_ZAWRS, EXT_INTERNAL_ZFH_MOVE, EXT_SMCSRIND, EXT_SSCSRIND, diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in index 6db6fa9..469c48d 100644 --- a/riscv/riscv.mk.in +++ b/riscv/riscv.mk.in @@ -987,6 +987,10 @@ riscv_insn_ext_zabha = \ amoxor_h \ amocas_h \ +riscv_insn_ext_zawrs = \ + wrs_sto \ + wrs_nto \ + riscv_insn_ext_zalasr = \ lb_aq \ lh_aq \ @@ -1099,6 +1103,7 @@ riscv_insn_list = \ $(riscv_insn_ext_q_zfa) \ $(riscv_insn_ext_zacas) \ $(riscv_insn_ext_zabha) \ + $(riscv_insn_ext_zawrs) \ $(riscv_insn_ext_zalasr) \ $(riscv_insn_ext_zce) \ $(riscv_insn_ext_zfh) \ |