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author | Andrew Waterman <aswaterman@gmail.com> | 2015-01-02 23:17:44 -0800 |
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committer | Andrew Waterman <aswaterman@gmail.com> | 2015-01-02 23:17:44 -0800 |
commit | c42146fbe46827af81fde8542212dc3c6e69aa57 (patch) | |
tree | b8b1a649086f9fc0d4ebf82e1e438567c32cadbe | |
parent | ec297672b0c9d58d1ee6c2ac976ccf28863bd3c2 (diff) | |
download | riscv-isa-sim-c42146fbe46827af81fde8542212dc3c6e69aa57.zip riscv-isa-sim-c42146fbe46827af81fde8542212dc3c6e69aa57.tar.gz riscv-isa-sim-c42146fbe46827af81fde8542212dc3c6e69aa57.tar.bz2 |
Require 4-byte instruction alignment until RVC is reimplemented
-rw-r--r-- | riscv/mmu.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index d24ed18..329f291 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -89,7 +89,8 @@ public: if (likely(entry->tag == addr)) return entry; - char* iaddr = (char*)translate(addr, 2, false, true); + bool rvc = false; // set this dynamically once RVC is re-implemented + char* iaddr = (char*)translate(addr, rvc ? 2 : 4, false, true); insn_bits_t insn = *(uint16_t*)iaddr; if (unlikely(insn_length(insn) == 2)) { |