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author | Andrew Waterman <andrew@sifive.com> | 2024-04-29 14:51:44 -0700 |
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committer | GitHub <noreply@github.com> | 2024-04-29 14:51:44 -0700 |
commit | bfe1d76608448ed668315b67723de538eac7ecb3 (patch) | |
tree | 21ea4697cbff217f26291adcddc8b91b6f514958 | |
parent | 0d1c3469e5e38bc45869d5efa86262a0d2893535 (diff) | |
parent | e53f9cb74c7f82f5de2e115cf3e53b853cb07812 (diff) | |
download | riscv-isa-sim-bfe1d76608448ed668315b67723de538eac7ecb3.zip riscv-isa-sim-bfe1d76608448ed668315b67723de538eac7ecb3.tar.gz riscv-isa-sim-bfe1d76608448ed668315b67723de538eac7ecb3.tar.bz2 |
Merge pull request #1579 from tebartsch/plic-threshold-masking
PLIC: Implement threshold masking
-rw-r--r-- | riscv/plic.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/riscv/plic.cc b/riscv/plic.cc index 44f80cf..01def70 100644 --- a/riscv/plic.cc +++ b/riscv/plic.cc @@ -113,6 +113,15 @@ uint32_t plic_t::context_best_pending(const plic_context_t *c) } } + /* + From Spec 1.0.0: 6. Priority Thresholds + The PLIC will mask all PLIC interrupts of a priority less than or equal to + threshold. + */ + if (best_id_prio <= c->priority_threshold) { + return 0; + } + return best_id; } |