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author | Tim Newsome <tim@sifive.com> | 2022-05-19 17:11:07 -0700 |
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committer | GitHub <noreply@github.com> | 2022-05-19 17:11:07 -0700 |
commit | a0298a33e7b2091ba8d9f3a20838d96dc1164cac (patch) | |
tree | f6227ea4d52123b92c7236616317fbba149e2733 | |
parent | 32eeb5a2b2ba6960f3379b23fa41b67ad0a4e38b (diff) | |
download | riscv-isa-sim-a0298a33e7b2091ba8d9f3a20838d96dc1164cac.zip riscv-isa-sim-a0298a33e7b2091ba8d9f3a20838d96dc1164cac.tar.gz riscv-isa-sim-a0298a33e7b2091ba8d9f3a20838d96dc1164cac.tar.bz2 |
Move ebreak* logic from take_trap into instructions. (#1006)
Now that logic only affects ebreak instructions, and does not affect
triggers that also cause a trap to be taken.
Fixes #725. Although like Paul, I don't have a test for this case.
Introduce trap_debug_mode so so ebreak instructions can force entry into
debug mode.
-rw-r--r-- | riscv/execute.cc | 4 | ||||
-rw-r--r-- | riscv/insns/c_ebreak.h | 9 | ||||
-rw-r--r-- | riscv/insns/ebreak.h | 9 | ||||
-rw-r--r-- | riscv/processor.cc | 8 | ||||
-rw-r--r-- | riscv/trap.h | 5 |
5 files changed, 25 insertions, 10 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index a6ea7a4..ea4dc5b 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -337,6 +337,10 @@ void processor_t::step(size_t n) abort(); } } + catch(trap_debug_mode&) + { + enter_debug_mode(DCSR_CAUSE_SWBP); + } catch (wait_for_interrupt_t &t) { // Return to the outer simulation loop, which gives other devices/harts a diff --git a/riscv/insns/c_ebreak.h b/riscv/insns/c_ebreak.h index 7d04f46..c8cc1f5 100644 --- a/riscv/insns/c_ebreak.h +++ b/riscv/insns/c_ebreak.h @@ -1,2 +1,9 @@ require_extension('C'); -throw trap_breakpoint(STATE.v, pc); +if (!STATE.debug_mode && + ((STATE.prv == PRV_M && STATE.dcsr->ebreakm) || + (STATE.prv == PRV_S && STATE.dcsr->ebreaks) || + (STATE.prv == PRV_U && STATE.dcsr->ebreaku))) { + throw trap_debug_mode(); +} else { + throw trap_breakpoint(STATE.v, pc); +} diff --git a/riscv/insns/ebreak.h b/riscv/insns/ebreak.h index 9f3d44d..227ab93 100644 --- a/riscv/insns/ebreak.h +++ b/riscv/insns/ebreak.h @@ -1 +1,8 @@ -throw trap_breakpoint(STATE.v, pc); +if (!STATE.debug_mode && + ((STATE.prv == PRV_M && STATE.dcsr->ebreakm) || + (STATE.prv == PRV_S && STATE.dcsr->ebreaks) || + (STATE.prv == PRV_U && STATE.dcsr->ebreaku))) { + throw trap_debug_mode(); +} else { + throw trap_breakpoint(STATE.v, pc); +} diff --git a/riscv/processor.cc b/riscv/processor.cc index a9003a8..bb41248 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -720,14 +720,6 @@ void processor_t::take_trap(trap_t& t, reg_t epc) return; } - if (t.cause() == CAUSE_BREAKPOINT && ( - (state.prv == PRV_M && state.dcsr->ebreakm) || - (state.prv == PRV_S && state.dcsr->ebreaks) || - (state.prv == PRV_U && state.dcsr->ebreaku))) { - enter_debug_mode(DCSR_CAUSE_SWBP); - return; - } - // By default, trap to M-mode, unless delegated to HS-mode or VS-mode reg_t vsdeleg, hsdeleg; reg_t bit = t.cause(); diff --git a/riscv/trap.h b/riscv/trap.h index 1cd62e1..8347c6e 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -8,6 +8,11 @@ struct state_t; +class trap_debug_mode +{ + /* Used to enter debug mode, which isn't quite a normal trap. */ +}; + class trap_t { public: |