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| author | YenHaoChen <howard25336284@gmail.com> | 2024-05-22 08:48:30 +0800 |
|---|---|---|
| committer | YenHaoChen <howard25336284@gmail.com> | 2024-05-22 09:04:23 +0800 |
| commit | 76579667170dd50dace957d0606a320094e0a2a4 (patch) | |
| tree | ef6fef4a75f6a88236a343be5cac6e217a112a14 | |
| parent | 5e2edf84ccc02303b549bd81345b4ac56655334f (diff) | |
| download | riscv-isa-sim-76579667170dd50dace957d0606a320094e0a2a4.zip riscv-isa-sim-76579667170dd50dace957d0606a320094e0a2a4.tar.gz riscv-isa-sim-76579667170dd50dace957d0606a320094e0a2a4.tar.bz2 | |
triggers: introduce tinfo.version
| -rw-r--r-- | riscv/triggers.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 9c81b89..1d0ed8b 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -631,7 +631,8 @@ reg_t module_t::tinfo_read(unsigned UNUSED index) const noexcept (1 << CSR_TDATA1_TYPE_ITRIGGER) | (1 << CSR_TDATA1_TYPE_ETRIGGER) | (1 << CSR_TDATA1_TYPE_MCONTROL6) | - (1 << CSR_TDATA1_TYPE_DISABLED); + (1 << CSR_TDATA1_TYPE_DISABLED) | + (CSR_TINFO_VERSION_1 << CSR_TINFO_VERSION_OFFSET); } }; |