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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-20 23:11:49 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-20 23:11:49 -0700 |
| commit | 6c965e11dc7950207f7cc0baff0ff273c33f4ecc (patch) | |
| tree | 80cf993dc14ed98b31f3784b1db17218a9d3ffc0 | |
| parent | bc5b666397b9dc3abd0012d31db061181062946e (diff) | |
| download | riscv-isa-sim-6c965e11dc7950207f7cc0baff0ff273c33f4ecc.zip riscv-isa-sim-6c965e11dc7950207f7cc0baff0ff273c33f4ecc.tar.gz riscv-isa-sim-6c965e11dc7950207f7cc0baff0ff273c33f4ecc.tar.bz2 | |
For misaligned fetch, set mepc = addr of branch/jump
| -rw-r--r-- | riscv/decode.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 2fdb042..4ad4549 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -153,7 +153,11 @@ private: #define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen)) #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen)) -#define set_pc(x) (npc = sext_xlen(x)) +#define set_pc(x) \ + do { if ((x) & 3 /* For now... */) \ + throw trap_instruction_address_misaligned(x); \ + npc = sext_xlen(x); \ + } while(0) #define validate_csr(which, write) ({ \ unsigned my_priv = get_field(STATE.mstatus, MSTATUS_PRV); \ |