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| author | Andrew Waterman <andrew@sifive.com> | 2024-02-19 13:56:44 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-02-19 13:56:44 -0800 |
| commit | 690298d792ce4c77d96a5e92070bb8553a0f461f (patch) | |
| tree | 9cb5241c50859be400c92aed20378fda9f851b87 | |
| parent | 066a3c1fb05653034fa5e05acc938f4200a161e0 (diff) | |
| parent | d16f8b06dd000d243c9ff29c374abc17124ae5a1 (diff) | |
| download | riscv-isa-sim-690298d792ce4c77d96a5e92070bb8553a0f461f.zip riscv-isa-sim-690298d792ce4c77d96a5e92070bb8553a0f461f.tar.gz riscv-isa-sim-690298d792ce4c77d96a5e92070bb8553a0f461f.tar.bz2 | |
Merge pull request #1602 from YenHaoChen/pr-c_lui
Fix c.mop.N decoding
| -rw-r--r-- | riscv/insns/c_lui.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/c_lui.h b/riscv/insns/c_lui.h index 3e0e02f..7a82c13 100644 --- a/riscv/insns/c_lui.h +++ b/riscv/insns/c_lui.h @@ -4,7 +4,7 @@ if (insn.rvc_rd() == 2) { // c.addi16sp WRITE_REG(X_SP, sext_xlen(RVC_SP + insn.rvc_addi16sp_imm())); } else if (insn.rvc_imm() != 0) { // c.lui WRITE_RD(insn.rvc_imm() << 12); -} else if ((insn.rvc_rd() & 1) != 0) { // c.mop.N +} else if ((insn.rvc_rd() & 0x11) == 1) { // c.mop.N #include "c_mop_N.h" } else { require(false); |