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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-21 20:35:19 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-21 20:45:57 -0700 |
| commit | 61c898734340ac0bad5a106684ba7565f4ee36d3 (patch) | |
| tree | 3b5748ff87a76754468945fff128f55b00f95f5d | |
| parent | 857ebb501199938327e9d25db45ccc13d646d4f6 (diff) | |
| download | riscv-isa-sim-61c898734340ac0bad5a106684ba7565f4ee36d3.zip riscv-isa-sim-61c898734340ac0bad5a106684ba7565f4ee36d3.tar.gz riscv-isa-sim-61c898734340ac0bad5a106684ba7565f4ee36d3.tar.bz2 | |
rvv: refine comparision checking
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/decode.h | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 5baef00..e3adc37 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -483,14 +483,12 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) } #define VI_CHECK_MSS(is_vs1) \ - if (P.VU.vflmul > 1) { \ - require_noover(insn.rd(), 1, insn.rs2(), P.VU.vflmul); \ - require_align(insn.rs2(), P.VU.vflmul); \ - if (is_vs1) {\ - require_noover(insn.rd(), 1, insn.rs1(), P.VU.vflmul); \ - require_align(insn.rs1(), P.VU.vflmul); \ - } \ - } + require_noover(insn.rd(), 1, insn.rs2(), P.VU.vflmul); \ + require_align(insn.rs2(), P.VU.vflmul); \ + if (is_vs1) {\ + require_noover(insn.rd(), 1, insn.rs1(), P.VU.vflmul); \ + require_align(insn.rs1(), P.VU.vflmul); \ + } \ #define VI_CHECK_SSS(is_vs1) \ require_vm; \ |