rvv: refine st_index

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

9 files changed, 18 insertions, 192 deletions

diff --git a/riscv/decode.h b/riscv/decode.h
index fac0fe3..8ece184 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -1632,7 +1632,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
   } \
   P.VU.vstart = 0;
 
-#define VI_ST_INDEX(stride, offset, st_width, is_seg) \
+#define VI_ST_INDEX(elt_width, is_seg) \
   VI_CHECK_ST_INDEX; \
   const reg_t nf = insn.v_nf() + 1; \
   const reg_t vl = P.VU.vl; \
@@ -1643,27 +1643,29 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \
   if (!is_seg) \
     require(nf == 1); \
   const reg_t vlmul = P.VU.vlmul; \
+  VI_DUPLICATE_VREG(insn.rs2(), elt_width);   \
   for (reg_t i = 0; i < vl; ++i) { \
     VI_STRIP(i) \
     VI_ELEMENT_SKIP(i); \
     for (reg_t fn = 0; fn < nf; ++fn) { \
-      st_width##_t val = 0; \
       switch (P.VU.vsew) { \
       case e8: \
-        val = P.VU.elt<uint8_t>(vs3 + fn * vlmul, vreg_inx); \
+        MMU.store_uint8(baseAddr + index[i] + fn * 1, \
+          P.VU.elt<uint8_t>(vs3 + fn * vlmul, vreg_inx)); \
         break; \
       case e16: \
-        val = P.VU.elt<uint16_t>(vs3 + fn * vlmul, vreg_inx); \
+        MMU.store_uint16(baseAddr + index[i] + fn * 2, \
+          P.VU.elt<uint16_t>(vs3 + fn * vlmul, vreg_inx)); \
         break; \
       case e32: \
-        val = P.VU.elt<uint32_t>(vs3 + fn * vlmul, vreg_inx); \
+        MMU.store_uint32(baseAddr + index[i] + fn * 4, \
+          P.VU.elt<uint32_t>(vs3 + fn * vlmul, vreg_inx)); \
         break; \
       default: \
-        val = P.VU.elt<uint64_t>(vs3 + fn * vlmul, vreg_inx); \
+        MMU.store_uint64(baseAddr + index[i] + fn * 8, \
+          P.VU.elt<uint64_t>(vs3 + fn * vlmul, vreg_inx)); \
         break; \
       } \
-      MMU.store_##st_width( \
-        baseAddr + (stride) + (offset) * sizeof(st_width##_t), val); \
     } \
   } \
   P.VU.vstart = 0;
diff --git a/riscv/insns/vsuxei16_v.h b/riscv/insns/vsuxei16_v.h
index 98435f6..f361c03 100644
--- a/riscv/insns/vsuxei16_v.h
+++ b/riscv/insns/vsuxei16_v.h
@@ -1,24 +1,2 @@
 // vsuxe16.v
-VI_DUPLICATE_VREG(insn.rs2(), 16);
-
-switch(P.VU.vsew) {
-  case e8: {
-      VI_ST_INDEX(index[i], fn, uint8, false);
-    }
-    break;
-  case e16: {
-      VI_ST_INDEX(index[i], fn, uint16, false);
-    }
-    break;
-  case e32: {
-      VI_ST_INDEX(index[i], fn, uint32, false);
-    }
-    break;
-  case e64: {
-      VI_ST_INDEX(index[i], fn, uint64, false);
-    }
-    break;
-  default:
-    require(0);
-    break;
-};
+VI_ST_INDEX(e16, false);
diff --git a/riscv/insns/vsuxei32_v.h b/riscv/insns/vsuxei32_v.h
index cdfb592..c1c8dc7 100644
--- a/riscv/insns/vsuxei32_v.h
+++ b/riscv/insns/vsuxei32_v.h
@@ -1,24 +1,2 @@
 // vsuxe32.v
-VI_DUPLICATE_VREG(insn.rs2(), 32);
-
-switch(P.VU.vsew) {
-  case e8: {
-      VI_ST_INDEX(index[i], fn, uint8, false);
-    }
-    break;
-  case e16: {
-      VI_ST_INDEX(index[i], fn, uint16, false);
-    }
-    break;
-  case e32: {
-      VI_ST_INDEX(index[i], fn, uint32, false);
-    }
-    break;
-  case e64: {
-      VI_ST_INDEX(index[i], fn, uint64, false);
-    }
-    break;
-  default:
-    require(0);
-    break;
-};
+VI_ST_INDEX(e32, false);
diff --git a/riscv/insns/vsuxei64_v.h b/riscv/insns/vsuxei64_v.h
index ed7cb50..0c619cf 100644
--- a/riscv/insns/vsuxei64_v.h
+++ b/riscv/insns/vsuxei64_v.h
@@ -1,24 +1,2 @@
 // vsuxe64.v
-VI_DUPLICATE_VREG(insn.rs2(), 64);
-
-switch(P.VU.vsew) {
-  case e8: {
-      VI_ST_INDEX(index[i], fn, uint8, false);
-    }
-    break;
-  case e16: {
-      VI_ST_INDEX(index[i], fn, uint16, false);
-    }
-    break;
-  case e32: {
-      VI_ST_INDEX(index[i], fn, uint32, false);
-    }
-    break;
-  case e64: {
-      VI_ST_INDEX(index[i], fn, uint64, false);
-    }
-    break;
-  default:
-    require(0);
-    break;
-};
+VI_ST_INDEX(e64, false);
diff --git a/riscv/insns/vsuxei8_v.h b/riscv/insns/vsuxei8_v.h
index ff7bde0..36d2a11 100644
--- a/riscv/insns/vsuxei8_v.h
+++ b/riscv/insns/vsuxei8_v.h
@@ -1,24 +1,2 @@
 // vsuxe8.v
-VI_DUPLICATE_VREG(insn.rs2(), 8);
-
-switch(P.VU.vsew) {
-  case e8: {
-      VI_ST_INDEX(index[i], fn, uint8, false);
-    }
-    break;
-  case e16: {
-      VI_ST_INDEX(index[i], fn, uint16, false);
-    }
-    break;
-  case e32: {
-      VI_ST_INDEX(index[i], fn, uint32, false);
-    }
-    break;
-  case e64: {
-      VI_ST_INDEX(index[i], fn, uint64, false);
-    }
-    break;
-  default:
-    require(0);
-    break;
-};
+VI_ST_INDEX(e8, false);
diff --git a/riscv/insns/vsxei16_v.h b/riscv/insns/vsxei16_v.h
index 72bb8e9..42c3c78 100644
--- a/riscv/insns/vsxei16_v.h
+++ b/riscv/insns/vsxei16_v.h
@@ -1,24 +1,2 @@
 // vsxei16.v and vsxseg[2-8]ei16.v
-VI_DUPLICATE_VREG(insn.rs2(), 16);
-
-switch(P.VU.vsew) {
-  case e8: {
-      VI_ST_INDEX(index[i], fn, uint8, true);
-    }
-    break;
-  case e16: {
-      VI_ST_INDEX(index[i], fn, uint16, true);
-    }
-    break;
-  case e32: {
-      VI_ST_INDEX(index[i], fn, uint32, true);
-    }
-    break;
-  case e64: {
-      VI_ST_INDEX(index[i], fn, uint64, true);
-    }
-    break;
-  default:
-    require(0);
-    break;
-};
+VI_ST_INDEX(e16, true);
diff --git a/riscv/insns/vsxei32_v.h b/riscv/insns/vsxei32_v.h
index 296c8bb..f0aed6b 100644
--- a/riscv/insns/vsxei32_v.h
+++ b/riscv/insns/vsxei32_v.h
@@ -1,24 +1,2 @@
 // vsxei32.v and vsxseg[2-8]ei32.v
-VI_DUPLICATE_VREG(insn.rs2(), 32);
-
-switch(P.VU.vsew) {
-  case e8: {
-      VI_ST_INDEX(index[i], fn, uint8, true);
-    }
-    break;
-  case e16: {
-      VI_ST_INDEX(index[i], fn, uint16, true);
-    }
-    break;
-  case e32: {
-      VI_ST_INDEX(index[i], fn, uint32, true);
-    }
-    break;
-  case e64: {
-      VI_ST_INDEX(index[i], fn, uint64, true);
-    }
-    break;
-  default:
-    require(0);
-    break;
-};
+VI_ST_INDEX(e32, true);
diff --git a/riscv/insns/vsxei64_v.h b/riscv/insns/vsxei64_v.h
index b5d286f..88ddaf3 100644
--- a/riscv/insns/vsxei64_v.h
+++ b/riscv/insns/vsxei64_v.h
@@ -1,24 +1,2 @@
 // vsxei64.v and vsxseg[2-8]ei64.v
-VI_DUPLICATE_VREG(insn.rs2(), 64);
-
-switch(P.VU.vsew) {
-  case e8: {
-      VI_ST_INDEX(index[i], fn, uint8, true);
-    }
-    break;
-  case e16: {
-      VI_ST_INDEX(index[i], fn, uint16, true);
-    }
-    break;
-  case e32: {
-      VI_ST_INDEX(index[i], fn, uint32, true);
-    }
-    break;
-  case e64: {
-      VI_ST_INDEX(index[i], fn, uint64, true);
-    }
-    break;
-  default:
-    require(0);
-    break;
-};
+VI_ST_INDEX(e64, true);
diff --git a/riscv/insns/vsxei8_v.h b/riscv/insns/vsxei8_v.h
index 355223c..621512c 100644
--- a/riscv/insns/vsxei8_v.h
+++ b/riscv/insns/vsxei8_v.h
@@ -1,24 +1,2 @@
 // vsxei8.v and vsxseg[2-8]ei8.v
-VI_DUPLICATE_VREG(insn.rs2(), 8);
-
-switch(P.VU.vsew) {
-  case e8: {
-      VI_ST_INDEX(index[i], fn, uint8, true);
-    }
-    break;
-  case e16: {
-      VI_ST_INDEX(index[i], fn, uint16, true);
-    }
-    break;
-  case e32: {
-      VI_ST_INDEX(index[i], fn, uint32, true);
-    }
-    break;
-  case e64: {
-      VI_ST_INDEX(index[i], fn, uint64, true);
-    }
-    break;
-  default:
-    require(0);
-    break;
-};
+VI_ST_INDEX(e8, true);