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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-20 00:14:42 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-05-20 00:14:42 -0700 |
| commit | 3f73156f2297763571e38701d89fdfa35a22aca2 (patch) | |
| tree | cea670685fc98429ebcbcc2812321697271251a5 | |
| parent | 67fc0f5d6be03929b412aa70d47236d67f68b769 (diff) | |
| download | riscv-isa-sim-3f73156f2297763571e38701d89fdfa35a22aca2.zip riscv-isa-sim-3f73156f2297763571e38701d89fdfa35a22aca2.tar.gz riscv-isa-sim-3f73156f2297763571e38701d89fdfa35a22aca2.tar.bz2 | |
rvv: remove debug
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
| -rw-r--r-- | riscv/decode.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 9eb4058..ef1b2fd 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -499,7 +499,6 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) require_noover(insn.rd(), P.VU.vflmul * 2, insn.rs2(), P.VU.vflmul); \ require_align(insn.rs2(), P.VU.vflmul); \ if (is_vs1) {\ - fprintf(stderr, "here 5\n"); \ require_noover(insn.rd(), P.VU.vflmul * 2, insn.rs1(), P.VU.vflmul); \ require_align(insn.rs1(), P.VU.vflmul); \ } |