diff options
| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-09-08 22:10:03 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-09-08 22:12:14 +0800 |
| commit | 25bca65b95d975d8f3bd4735483a4a3ee5c38440 (patch) | |
| tree | fe4f01448080be1638b122ee18917a66fff9e2da | |
| parent | d85446f81f3c9405a2041ab5235281a3bbaab77f (diff) | |
| download | riscv-isa-sim-25bca65b95d975d8f3bd4735483a4a3ee5c38440.zip riscv-isa-sim-25bca65b95d975d8f3bd4735483a4a3ee5c38440.tar.gz riscv-isa-sim-25bca65b95d975d8f3bd4735483a4a3ee5c38440.tar.bz2 | |
Remove redundant require_vm in macro VI_VV_LOOP_WITH_CARRY
and VI_XI_LOOP_WITH_CARRY: require_vm is also included in
VI_CHECK_SSS
| -rw-r--r-- | riscv/v_ext_macros.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/riscv/v_ext_macros.h b/riscv/v_ext_macros.h index 2893306..afc4837 100644 --- a/riscv/v_ext_macros.h +++ b/riscv/v_ext_macros.h @@ -1079,7 +1079,6 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) VI_LOOP_CARRY_END #define VI_VV_LOOP_WITH_CARRY(BODY) \ - require_vm; \ VI_CHECK_SSS(true); \ VI_LOOP_WITH_CARRY_BASE \ if (sew == e8) { \ @@ -1098,7 +1097,6 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) VI_LOOP_END #define VI_XI_LOOP_WITH_CARRY(BODY) \ - require_vm; \ VI_CHECK_SSS(false); \ VI_LOOP_WITH_CARRY_BASE \ if (sew == e8) { \ |