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| author | Andrew Waterman <andrew@sifive.com> | 2023-06-07 21:13:36 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-06-07 21:13:36 -0700 |
| commit | 08053dc9478dd43a4969697e55de62b8b4c4922f (patch) | |
| tree | 78babec39ae45b1405c72d1a25e16bb99536ac2f | |
| parent | 97fbfec1c21895ccf0b82f777fba684457fde8fe (diff) | |
| parent | cf7e434c8005fc79f563be98542aa1d42a85f869 (diff) | |
| download | riscv-isa-sim-08053dc9478dd43a4969697e55de62b8b4c4922f.zip riscv-isa-sim-08053dc9478dd43a4969697e55de62b8b4c4922f.tar.gz riscv-isa-sim-08053dc9478dd43a4969697e55de62b8b4c4922f.tar.bz2 | |
Merge pull request #1375 from demin-han/master
Replace ternary operator with std:min
| -rw-r--r-- | riscv/vector_unit.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/vector_unit.cc b/riscv/vector_unit.cc index ff3dd82..9128df6 100644 --- a/riscv/vector_unit.cc +++ b/riscv/vector_unit.cc @@ -54,11 +54,11 @@ reg_t vectorUnit_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t new if (vlmax == 0) { vl->write_raw(0); } else if (rd == 0 && rs1 == 0) { - vl->write_raw(vl->read() > vlmax ? vlmax : vl->read()); + vl->write_raw(std::min(vl->read(), vlmax)); } else if (rd != 0 && rs1 == 0) { vl->write_raw(vlmax); } else if (rs1 != 0) { - vl->write_raw(reqVL > vlmax ? vlmax : reqVL); + vl->write_raw(std::min(reqVL, vlmax)); } vstart->write_raw(0); |