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| author | Scott Johnson <scott.johnson@arilinc.com> | 2023-04-27 13:26:04 -0700 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2024-01-11 17:43:17 -0800 |
| commit | 073510dbd46f53a71b09633a802fcd97ee38a3ac (patch) | |
| tree | 4930613fbda5953844bc7c995d9d6add314b19e3 | |
| parent | 7ed22f01fc8590582d75aa46adaf76409fc198f6 (diff) | |
| download | riscv-isa-sim-073510dbd46f53a71b09633a802fcd97ee38a3ac.zip riscv-isa-sim-073510dbd46f53a71b09633a802fcd97ee38a3ac.tar.gz riscv-isa-sim-073510dbd46f53a71b09633a802fcd97ee38a3ac.tar.bz2 | |
Introduce adjusted_cause which I will reuse next
| -rw-r--r-- | riscv/processor.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index f9c1a66..d02c6d5 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -878,9 +878,10 @@ void processor_t::take_trap(trap_t& t, reg_t epc) } if (state.prv <= PRV_S && bit < max_xlen && ((vsdeleg >> bit) & 1)) { // Handle the trap in VS-mode + const reg_t adjusted_cause = interrupt ? bit - 1 : bit; // VSSIP -> SSIP, etc reg_t vector = (state.vstvec->read() & 1) && interrupt ? 4 * bit : 0; state.pc = (state.vstvec->read() & ~(reg_t)1) + vector; - state.vscause->write((interrupt) ? (t.cause() - 1) : t.cause()); + state.vscause->write(adjusted_cause | (interrupt ? interrupt_bit : 0)); state.vsepc->write(epc); state.vstval->write(t.get_tval()); |