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author | Anup Patel <anup.patel@wdc.com> | 2020-11-28 14:49:03 +0530 |
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committer | Anup Patel <anup@brainfault.org> | 2020-11-28 14:49:03 +0530 |
commit | d0d923ebdef92deb26ac0f02fb15e61e328c602a (patch) | |
tree | 59d990f39ad60943bcc8a0a6f0d4192ab2407f2e | |
parent | 457f628ad78efa305283ae6cc4dc1530fceffbe4 (diff) | |
download | riscv-isa-sim-d0d923ebdef92deb26ac0f02fb15e61e328c602a.zip riscv-isa-sim-d0d923ebdef92deb26ac0f02fb15e61e328c602a.tar.gz riscv-isa-sim-d0d923ebdef92deb26ac0f02fb15e61e328c602a.tar.bz2 |
Fix typo in HTVAL CSR write emulation
We are saving new HTVAL value in wrong location for HTVAL CSR write
so let's fix this.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
-rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index e01e196..9cfd4ad 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -1142,7 +1142,7 @@ void processor_t::set_csr(int which, reg_t val) /* Ignore */ break; case CSR_HTVAL: - state.htinst = val; + state.htval = val; break; case CSR_HIP: { reg_t mask = MIP_VSSIP; |