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| author | Andrew Waterman <andrew@sifive.com> | 2020-12-04 10:27:28 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-04 10:27:28 -0800 |
| commit | a760df2d3226944a71eb117eaa8dd29248e1497d (patch) | |
| tree | 2d0e51e7b99b7663a784614ecbbb2ed03265142d | |
| parent | 21458a27101aeda7abd498f4c48a2192b0fef62f (diff) | |
| parent | b8c05a222d6adf04d8a0d032b30b9c29d958d768 (diff) | |
| download | riscv-isa-sim-a760df2d3226944a71eb117eaa8dd29248e1497d.zip riscv-isa-sim-a760df2d3226944a71eb117eaa8dd29248e1497d.tar.gz riscv-isa-sim-a760df2d3226944a71eb117eaa8dd29248e1497d.tar.bz2 | |
Merge pull request #613 from chihminchao/rvv-fix-2020-12-04
Rvv fix 2020 12 04
| -rw-r--r-- | riscv/decode.h | 1 | ||||
| -rw-r--r-- | riscv/processor.cc | 2 | ||||
| -rw-r--r-- | riscv/processor.h | 1 |
3 files changed, 3 insertions, 1 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 98d9dea..6878e15 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -1864,6 +1864,7 @@ for (reg_t i = 0; i < P.VU.vlmax && P.VU.vl != 0; ++i) { \ require_vm; \ reg_t from = P.VU.vsew / div; \ require(from >= e8 && from <= e64); \ + require(((float)P.VU.vflmul / div) >= ((float)P.VU.vsew_min / P.VU.ELEN)); \ require_align(insn.rd(), P.VU.vflmul); \ require_align(insn.rs2(), P.VU.vflmul / div); \ if ((P.VU.vflmul / div) < 1) { \ diff --git a/riscv/processor.cc b/riscv/processor.cc index 9cfd4ad..76a5417 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -397,7 +397,7 @@ reg_t processor_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t newT vill = !(vflmul >= 0.125 && vflmul <= 8) || vsew > ELEN - || vflmul < ((float)vsew / ELEN) + || vflmul < ((float)vsew_min / ELEN) || vediv != 1 || (newType >> 8) != 0; diff --git a/riscv/processor.h b/riscv/processor.h index 74ad526..3e6b3e9 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -488,6 +488,7 @@ public: reg_t vstart, vxrm, vxsat, vl, vtype, vlenb; reg_t vma, vta; reg_t vediv, vsew; + const reg_t vsew_min = 8; // the narrowest supported SEW value at LMUL=1 float vflmul; reg_t ELEN, VLEN; bool vill; |