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| author | Marcus Comstedt <marcus@mc.pp.se> | 2020-11-24 01:04:58 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-11-23 16:04:58 -0800 |
| commit | a73e43f2316e0e431ea6371e140c4007aa66fd89 (patch) | |
| tree | 90595bd2707ef7b332722c41684c1a65d7e2ac1a | |
| parent | 8be5c086bdf17b1a6813bfa3bb8a8993a07675ca (diff) | |
| download | riscv-isa-sim-a73e43f2316e0e431ea6371e140c4007aa66fd89.zip riscv-isa-sim-a73e43f2316e0e431ea6371e140c4007aa66fd89.tar.gz riscv-isa-sim-a73e43f2316e0e431ea6371e140c4007aa66fd89.tar.bz2 | |
Fix misaligned loads and stores for big endian target (#602)
| -rw-r--r-- | riscv/mmu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 5481946..4bba5b0 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -63,7 +63,7 @@ public: #ifdef RISCV_ENABLE_MISALIGNED reg_t res = 0; for (size_t i = 0; i < size; i++) - res += (reg_t)load_uint8(addr + i) << (i * 8); + res += (reg_t)load_uint8(addr + (target_big_endian? size-1-i : i)) << (i * 8); return res; #else throw trap_load_address_misaligned(addr, 0, 0); @@ -74,7 +74,7 @@ public: { #ifdef RISCV_ENABLE_MISALIGNED for (size_t i = 0; i < size; i++) - store_uint8(addr + i, data >> (i * 8)); + store_uint8(addr + (target_big_endian? size-1-i : i), data >> (i * 8)); #else throw trap_store_address_misaligned(addr, 0, 0); #endif |