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| author | Yunsup Lee <yunsup@sifive.com> | 2017-03-31 19:14:19 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@sifive.com> | 2017-03-31 19:15:41 -0700 |
| commit | f2e8eb28cca2a5f49cea9f37774058718f795fdd (patch) | |
| tree | c1d88742bb633d0838efb8cc277f0d3255fdb639 | |
| parent | 32f8b0bbb8dc0d9091a77eabfa476a2c4e0fd166 (diff) | |
| download | riscv-isa-sim-f2e8eb28cca2a5f49cea9f37774058718f795fdd.zip riscv-isa-sim-f2e8eb28cca2a5f49cea9f37774058718f795fdd.tar.gz riscv-isa-sim-f2e8eb28cca2a5f49cea9f37774058718f795fdd.tar.bz2 | |
update encoding.h to get PMP updates
| -rw-r--r-- | riscv/encoding.h | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/riscv/encoding.h b/riscv/encoding.h index b07d976..55f8461 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -127,13 +127,14 @@ #define PMP_R 0x01 #define PMP_W 0x02 #define PMP_X 0x04 -#define PMP_M 0x08 -#define PMP_NAPOT 0x10 -#define PMP_TOR 0x20 -#define PMP_EN 0x40 -#define PMP_LOCK 0x80 +#define PMP_A 0x18 +#define PMP_L 0x80 #define PMP_SHIFT 2 +#define PMP_TOR 0x08 +#define PMP_NA4 0x10 +#define PMP_NAPOT 0x18 + #define IRQ_S_SOFT 1 #define IRQ_H_SOFT 2 #define IRQ_M_SOFT 3 |