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author | Andrew Waterman <andrew@sifive.com> | 2017-01-07 18:03:16 -0800 |
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committer | Andrew Waterman <andrew@sifive.com> | 2017-01-07 18:03:16 -0800 |
commit | e9e30598e08e4f162b523f9ef07f1510f3cfe0a6 (patch) | |
tree | 058cad42034c56faba94ef524238f65589ce36e2 | |
parent | b387326dbc6b4bf2452191b6817529133ff362a5 (diff) | |
download | riscv-isa-sim-e9e30598e08e4f162b523f9ef07f1510f3cfe0a6.zip riscv-isa-sim-e9e30598e08e4f162b523f9ef07f1510f3cfe0a6.tar.gz riscv-isa-sim-e9e30598e08e4f162b523f9ef07f1510f3cfe0a6.tar.bz2 |
Only allow SIP.SSIP to be toggled if the interrupt is delegated
-rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 75f4002..7417acf 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -374,7 +374,7 @@ void processor_t::set_csr(int which, reg_t val) return set_csr(CSR_MSTATUS, (state.mstatus & ~mask) | (val & mask)); } case CSR_SIP: { - reg_t mask = MIP_SSIP; + reg_t mask = MIP_SSIP & state.mideleg; return set_csr(CSR_MIP, (state.mip & ~mask) | (val & mask)); } case CSR_SIE: |