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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-23 13:24:10 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-23 13:24:10 -0700 |
| commit | e83a032060865550e33659a69a86870f9da880b1 (patch) | |
| tree | 7efabd7b1f8da0533119c2c0a23dbabb5e8d6b0a | |
| parent | 46f1423c6566aee512fbc7a8ef6ff4aae2b7d1fb (diff) | |
| download | riscv-isa-sim-e83a032060865550e33659a69a86870f9da880b1.zip riscv-isa-sim-e83a032060865550e33659a69a86870f9da880b1.tar.gz riscv-isa-sim-e83a032060865550e33659a69a86870f9da880b1.tar.bz2 | |
Require little-endian host
| -rw-r--r-- | riscv/decode.h | 4 | ||||
| -rw-r--r-- | riscv/encoding.h | 10 |
2 files changed, 14 insertions, 0 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index d82767d..061b5b6 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -7,6 +7,10 @@ # error spike requires a two''s-complement c++ implementation #endif +#ifdef WORDS_BIGENDIAN +# error spike requires a little-endian host +#endif + #include <cstdint> #include <string.h> #include <strings.h> diff --git a/riscv/encoding.h b/riscv/encoding.h index 3923bff..a7066b7 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -124,6 +124,16 @@ #define SPTBR_MODE_SV57 10 #define SPTBR_MODE_SV64 11 +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_M 0x08 +#define PMP_NAPOT 0x10 +#define PMP_TOR 0x20 +#define PMP_EN 0x40 +#define PMP_LOCK 0x80 +#define PMP_SHIFT 2 + #define IRQ_S_SOFT 1 #define IRQ_H_SOFT 2 #define IRQ_M_SOFT 3 |