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| author | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-30 00:02:49 -0700 |
|---|---|---|
| committer | Wesley W. Terpstra <wesley@sifive.com> | 2017-03-30 00:02:49 -0700 |
| commit | b04dfe31de85923faf4c701ec2fcf7ff0afc6de7 (patch) | |
| tree | e3efb0a27566e8b2720351ed9b51f7d5622aa47b | |
| parent | 7b396b51a6c38bc3472ea9c995e8015b39f19c1f (diff) | |
| download | riscv-isa-sim-b04dfe31de85923faf4c701ec2fcf7ff0afc6de7.zip riscv-isa-sim-b04dfe31de85923faf4c701ec2fcf7ff0afc6de7.tar.gz riscv-isa-sim-b04dfe31de85923faf4c701ec2fcf7ff0afc6de7.tar.bz2 | |
fdt: move interrupt controller into its own node
| -rw-r--r-- | riscv/sim.cc | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index cb1ed71..7a10c9b 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -271,8 +271,11 @@ void sim_t::make_dtb() " riscv,isa = \"" << procs[i]->isa_string << "\";\n" " mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n" " clock-frequency = <" << CPU_HZ << ">;\n" - " interrupt-controller;\n" - " #interrupt-cells = <1>;\n" + " CPU" << i << "_intc: interrupt-controller {\n" + " #interrupt-cells = <1>;\n" + " interrupt-controller;\n" + " compatible = \"riscv,cpu-intc\";\n" + " };\n" " };\n"; } reg_t membs = DRAM_BASE; @@ -286,13 +289,13 @@ void sim_t::make_dtb() " soc {\n" " #address-cells = <2>;\n" " #size-cells = <2>;\n" - " compatible = \"ucbbar,spike-bare-soc\";\n" + " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n" " ranges;\n" " clint@" << CLINT_BASE << " {\n" " compatible = \"riscv,clint0\";\n" " interrupts-extended = <" << std::dec; for (size_t i = 0; i < procs.size(); i++) - s << "&CPU" << i << " 3 &CPU" << i << " 7 "; + s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 "; reg_t clintbs = CLINT_BASE; reg_t clintsz = CLINT_SIZE; s << std::hex << ">;\n" |