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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-27 21:21:57 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-27 21:21:57 -0700 |
| commit | 8f4fb411b016846a539a1ff1cd645a555e3737be (patch) | |
| tree | bdd4c84e0c370f5a27aa565783d298d7a8e10396 | |
| parent | a80c695b1961ac40086494920f82e85a085ff358 (diff) | |
| download | riscv-isa-sim-8f4fb411b016846a539a1ff1cd645a555e3737be.zip riscv-isa-sim-8f4fb411b016846a539a1ff1cd645a555e3737be.tar.gz riscv-isa-sim-8f4fb411b016846a539a1ff1cd645a555e3737be.tar.bz2 | |
On EBREAK, set badaddr to pc
| -rw-r--r-- | riscv/insns/c_ebreak.h | 2 | ||||
| -rw-r--r-- | riscv/insns/ebreak.h | 2 | ||||
| -rw-r--r-- | riscv/trap.h | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/riscv/insns/c_ebreak.h b/riscv/insns/c_ebreak.h index a17200f..128b86b 100644 --- a/riscv/insns/c_ebreak.h +++ b/riscv/insns/c_ebreak.h @@ -1,2 +1,2 @@ require_extension('C'); -throw trap_breakpoint(); +throw trap_breakpoint(pc); diff --git a/riscv/insns/ebreak.h b/riscv/insns/ebreak.h index c22776c..736cebe 100644 --- a/riscv/insns/ebreak.h +++ b/riscv/insns/ebreak.h @@ -1 +1 @@ -throw trap_breakpoint(); +throw trap_breakpoint(pc); diff --git a/riscv/trap.h b/riscv/trap.h index a289a68..20313e9 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -47,7 +47,7 @@ class mem_trap_t : public trap_t DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned) DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault) DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction) -DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint) +DECLARE_MEM_TRAP(CAUSE_BREAKPOINT, breakpoint) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned) DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned) DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault) |