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| author | Andrew Waterman <andrew@sifive.com> | 2017-05-05 14:39:26 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-05-05 14:39:26 -0700 |
| commit | 8a428c769bbde9997551596e324b1f70a66cf6ec (patch) | |
| tree | 391e061313463a370ff0528c20080d28755d8adc | |
| parent | 63c98b41ae2d36808ebbb57e7f8e871ba247d444 (diff) | |
| download | riscv-isa-sim-8a428c769bbde9997551596e324b1f70a66cf6ec.zip riscv-isa-sim-8a428c769bbde9997551596e324b1f70a66cf6ec.tar.gz riscv-isa-sim-8a428c769bbde9997551596e324b1f70a66cf6ec.tar.bz2 | |
Trap superpage PTEs when PPN LSBs are set
| -rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index f0adb22..76a6ab1 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -197,6 +197,8 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode) type == LOAD ? !(pte & PTE_R) && !(mxr && (pte & PTE_X)) : !((pte & PTE_R) && (pte & PTE_W))) { break; + } else if ((ppn & ((reg_t(1) << ptshift) - 1)) != 0) { + break; } else { reg_t ad = PTE_A | ((type == STORE) * PTE_D); #ifdef RISCV_ENABLE_DIRTY |