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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-24 18:10:41 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-24 18:10:41 -0700 |
| commit | 1fa2174178a5432443f114dfc059ba19c53b1fae (patch) | |
| tree | ef4f609e1d1d1e48350c9f22f9ca4b98bc435d6b | |
| parent | e83a032060865550e33659a69a86870f9da880b1 (diff) | |
| download | riscv-isa-sim-1fa2174178a5432443f114dfc059ba19c53b1fae.zip riscv-isa-sim-1fa2174178a5432443f114dfc059ba19c53b1fae.tar.gz riscv-isa-sim-1fa2174178a5432443f114dfc059ba19c53b1fae.tar.bz2 | |
Default to 2 GiB of memory
| -rw-r--r-- | riscv/sim.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc index e1a8540..cb1ed71 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -34,7 +34,7 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted, size_t memsz0 = (size_t)mem_mb << 20; size_t quantum = 1L << 20; if (memsz0 == 0) - memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20; + memsz0 = (size_t)2048 << 20; memsz = memsz0; while ((mem = (char*)calloc(1, memsz)) == NULL) |