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author | Tim Newsome <tim@sifive.com> | 2022-11-15 10:20:49 -0800 |
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committer | Tim Newsome <tim@sifive.com> | 2022-11-15 10:49:09 -0800 |
commit | e81c0528a3182f96b06307c6903fbf9b108e22bd (patch) | |
tree | 45c9ac4d5eacd68fbfc1f94970d3e76fe4f34437 | |
parent | 393f78346bebd6cb7ac2c88986262ef207c5b963 (diff) | |
download | riscv-isa-sim-e81c0528a3182f96b06307c6903fbf9b108e22bd.zip riscv-isa-sim-e81c0528a3182f96b06307c6903fbf9b108e22bd.tar.gz riscv-isa-sim-e81c0528a3182f96b06307c6903fbf9b108e22bd.tar.bz2 |
trigger_t: Protect destructor and memory_access_match()
-rw-r--r-- | riscv/triggers.h | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/riscv/triggers.h b/riscv/triggers.h index 3e91bab..bb000eb 100644 --- a/riscv/triggers.h +++ b/riscv/triggers.h @@ -42,8 +42,7 @@ class matched_t class trigger_t { public: - virtual match_result_t memory_access_match(processor_t * const proc, - operation_t operation, reg_t address, std::optional<reg_t> data) = 0; + virtual ~trigger_t() {}; virtual reg_t tdata1_read(const processor_t * const proc) const noexcept = 0; virtual bool tdata1_write(processor_t * const proc, const reg_t val) noexcept = 0; @@ -57,10 +56,8 @@ public: virtual bool get_load() const { return false; } virtual action_t get_action() const { return ACTION_DEBUG_EXCEPTION; } - virtual ~trigger_t() {}; - -protected: - trigger_t() {} + virtual match_result_t memory_access_match(processor_t * const proc, + operation_t operation, reg_t address, std::optional<reg_t> data) = 0; }; class tdata2_csr_t : public virtual trigger_t { @@ -100,7 +97,6 @@ public: private: bool simple_match(unsigned xlen, reg_t value) const; -public: bool dmode = false; action_t action = ACTION_DEBUG_EXCEPTION; bool hit = false; |