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| author | Tim Newsome <tim@sifive.com> | 2022-11-15 09:58:07 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-11-15 10:49:09 -0800 |
| commit | b231c3c3e5e45a06ce08e8f5080e64742aba8b37 (patch) | |
| tree | 32311986a143f387de791698ce8f4280487eb07f | |
| parent | e2323efbde19c6e44c123bf262e05296de178891 (diff) | |
| download | riscv-isa-sim-b231c3c3e5e45a06ce08e8f5080e64742aba8b37.zip riscv-isa-sim-b231c3c3e5e45a06ce08e8f5080e64742aba8b37.tar.gz riscv-isa-sim-b231c3c3e5e45a06ce08e8f5080e64742aba8b37.tar.bz2 | |
triggers: Rename/move dmode
dmode() -> get_dmode()
trigger_t.dmode_bit -> mcontrol_t.dmode
| -rw-r--r-- | riscv/triggers.cc | 8 | ||||
| -rw-r--r-- | riscv/triggers.h | 4 |
2 files changed, 7 insertions, 5 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 199a163..eae5e36 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -10,7 +10,7 @@ reg_t tdata2_csr_t::tdata2_read(const processor_t UNUSED * const proc) const noe } bool tdata2_csr_t::tdata2_write(processor_t * const proc, const reg_t val) noexcept { - if (dmode && !proc->get_state()->debug_mode) { + if (get_dmode() && !proc->get_state()->debug_mode) { return false; } tdata2 = val; @@ -39,9 +39,6 @@ reg_t mcontrol_t::tdata1_read(const processor_t * const proc) const noexcept { } bool mcontrol_t::tdata1_write(processor_t * const proc, const reg_t val) noexcept { - if (dmode && !proc->get_state()->debug_mode) { - return false; - } auto xlen = proc->get_xlen(); dmode = get_field(val, MCONTROL_DMODE(xlen)); hit = get_field(val, CSR_MCONTROL_HIT); @@ -191,6 +188,9 @@ reg_t module_t::tdata1_read(const processor_t * const proc, unsigned index) cons bool module_t::tdata1_write(processor_t * const proc, unsigned index, const reg_t val) noexcept { + if (triggers[index]->get_dmode() && !proc->get_state()->debug_mode) { + return false; + } bool result = triggers[index]->tdata1_write(proc, val); proc->trigger_updated(triggers); return result; diff --git a/riscv/triggers.h b/riscv/triggers.h index cff45f6..d2cb186 100644 --- a/riscv/triggers.h +++ b/riscv/triggers.h @@ -51,11 +51,11 @@ public: virtual bool tdata2_write(processor_t * const proc, const reg_t val) noexcept = 0; virtual bool chain() const { return false; } + virtual bool get_dmode() const = 0; virtual bool get_execute() const { return false; } virtual bool get_store() const { return false; } virtual bool get_load() const { return false; } - bool dmode = false; action_t action = ACTION_DEBUG_EXCEPTION; bool hit = false; @@ -90,6 +90,7 @@ public: virtual bool tdata1_write(processor_t * const proc, const reg_t val) noexcept override; virtual bool chain() const override { return chain_bit; } + virtual bool get_dmode() const override { return dmode; } virtual bool get_execute() const override { return execute; } virtual bool get_store() const override { return store; } virtual bool get_load() const override { return load; } @@ -101,6 +102,7 @@ private: bool simple_match(unsigned xlen, reg_t value) const; public: + bool dmode = false; bool select = false; bool timing = false; bool chain_bit = false; |