Merge pull request #1125 from riscv-software-src/cbo-fixes

Fix tval reporting for CBOs; constrain cache-block sizes to reasonable values

2 files changed, 8 insertions, 6 deletions

diff --git a/riscv/mmu.h b/riscv/mmu.h
index da84adc..1e5260b 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -199,8 +199,7 @@ public:
 
   void clean_inval(reg_t addr, bool clean, bool inval) {
     convert_load_traps_to_store_traps({
-      const reg_t vaddr = addr & ~(blocksz - 1);
-      const reg_t paddr = translate(vaddr, blocksz, LOAD, 0);
+      const reg_t paddr = translate(addr, blocksz, LOAD, 0) & ~(blocksz - 1);
       if (sim->addr_to_mem(paddr)) {
         if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
           tracer.clean_invalidate(paddr, blocksz, clean, inval);
@@ -342,7 +341,7 @@ public:
     return target_big_endian? target_endian<T>::to_be(n) : target_endian<T>::to_le(n);
   }
 
-  void set_cache_blocksz(uint64_t size)
+  void set_cache_blocksz(reg_t size)
   {
     blocksz = size;
   }
@@ -353,7 +352,7 @@ private:
   memtracer_list_t tracer;
   reg_t load_reservation_address;
   uint16_t fetch_temp;
-  uint64_t blocksz;
+  reg_t blocksz;
 
   // implement an instruction cache for simulator performance
   icache_entry_t icache[ICACHE_ENTRIES];
diff --git a/spike_main/spike.cc b/spike_main/spike.cc
index 933f626..20afac9 100644
--- a/spike_main/spike.cc
+++ b/spike_main/spike.cc
@@ -411,8 +411,11 @@ int main(int argc, char** argv)
   });
   parser.option(0, "blocksz", 1, [&](const char* s){
     blocksz = strtoull(s, 0, 0);
-    if (((blocksz & (blocksz - 1))) != 0) {
-      fprintf(stderr, "--blocksz should be power of 2\n");
+    const unsigned min_blocksz = 16;
+    const unsigned max_blocksz = PGSIZE;
+    if (blocksz < min_blocksz || blocksz > max_blocksz || ((blocksz & (blocksz - 1))) != 0) {
+      fprintf(stderr, "--blocksz must be a power of 2 between %u and %u\n",
+        min_blocksz, max_blocksz);
       exit(-1);
     }
   });