diff options
| author | Andrew Waterman <andrew@sifive.com> | 2022-10-19 17:47:28 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-19 21:12:25 -0700 |
| commit | 635985515fa7877b7fc7d5138e73abf32810afd1 (patch) | |
| tree | 1a98c04c4f5e4fc30449acf788778a33e0f77656 | |
| parent | 5cdb39484c531814a6640c1ec976a61d2ad21333 (diff) | |
| download | riscv-isa-sim-635985515fa7877b7fc7d5138e73abf32810afd1.zip riscv-isa-sim-635985515fa7877b7fc7d5138e73abf32810afd1.tar.gz riscv-isa-sim-635985515fa7877b7fc7d5138e73abf32810afd1.tar.bz2 | |
Simplify check_load_reservation
Invoking refill_tlb to get the physical address is somewhat baroque,
and not even helpful in practice, since successful SCs will fill
the TLB anyway.
| -rw-r--r-- | riscv/mmu.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 9858f55..45eb829 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -231,8 +231,8 @@ public: } reg_t paddr = translate(vaddr, 1, STORE, 0); - if (auto host_addr = sim->addr_to_mem(paddr)) - return load_reservation_address == refill_tlb(vaddr, paddr, host_addr, STORE).target_offset + vaddr; + if (sim->addr_to_mem(paddr)) + return load_reservation_address == paddr; else throw trap_store_access_fault((proc) ? proc->state.v : false, vaddr, 0, 0); // disallow SC to I/O space } |