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| author | Andrew Waterman <andrew@sifive.com> | 2022-10-17 17:22:05 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-17 17:22:05 -0700 |
| commit | 3f1b236707772f062b2df98dd4998ec2833d8b16 (patch) | |
| tree | bf809ea4370f293c6c8883ea0158406685e13373 | |
| parent | a82ef286216bad81db9477c1c8bc13bb48d6561c (diff) | |
| download | riscv-isa-sim-3f1b236707772f062b2df98dd4998ec2833d8b16.zip riscv-isa-sim-3f1b236707772f062b2df98dd4998ec2833d8b16.tar.gz riscv-isa-sim-3f1b236707772f062b2df98dd4998ec2833d8b16.tar.bz2 | |
fix clang build
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index d790d3f..9262199 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -769,7 +769,7 @@ const char* processor_t::get_privilege_string() case 0x3: return "M"; } } - fprintf(stderr, "Invalid prv=%lx v=%x\n", state.prv, state.v); + fprintf(stderr, "Invalid prv=%lx v=%x\n", (unsigned long)state.prv, state.v); abort(); } |