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| author | Andrew Waterman <andrew@sifive.com> | 2022-10-19 16:44:13 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-19 21:12:25 -0700 |
| commit | 1caaaa5471122885cf35c7f87a2ffaf687969dfe (patch) | |
| tree | 2e19f945301563df9e9192cc188a6ad2b67065e9 | |
| parent | 24907dfbd11210de62fadec7a8824f8c51eb07a6 (diff) | |
| download | riscv-isa-sim-1caaaa5471122885cf35c7f87a2ffaf687969dfe.zip riscv-isa-sim-1caaaa5471122885cf35c7f87a2ffaf687969dfe.tar.gz riscv-isa-sim-1caaaa5471122885cf35c7f87a2ffaf687969dfe.tar.bz2 | |
No need to require_alignment for the load part of the AMO
The earlier call to store_slow_path will catch the misalignment.
| -rw-r--r-- | riscv/mmu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.h b/riscv/mmu.h index 479d9d3..ac3fb6f 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -148,7 +148,7 @@ public: type##_t amo_##type(reg_t addr, op f) { \ convert_load_traps_to_store_traps({ \ store_slow_path(addr, sizeof(type##_t), nullptr, 0, false, true); \ - auto lhs = load_##type(addr, true); \ + auto lhs = load_##type(addr); \ store_##type(addr, f(lhs)); \ return lhs; \ }) \ |