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| author | Tim Newsome <tim@sifive.com> | 2022-11-15 09:35:32 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-11-15 10:44:02 -0800 |
| commit | 1544d4e283c29798b449dd4fda0a6865e68c2af3 (patch) | |
| tree | 0449b5ad978db76ee6f94d2b3805d904b0141294 | |
| parent | 1319e98c10e96a1da9762caf55ce8132a27c4cfe (diff) | |
| download | riscv-isa-sim-1544d4e283c29798b449dd4fda0a6865e68c2af3.zip riscv-isa-sim-1544d4e283c29798b449dd4fda0a6865e68c2af3.tar.gz riscv-isa-sim-1544d4e283c29798b449dd4fda0a6865e68c2af3.tar.bz2 | |
Triggers rename execute
execute() -> get_execute(), execute_bit -> execute
| -rw-r--r-- | riscv/processor.cc | 2 | ||||
| -rw-r--r-- | riscv/triggers.cc | 8 | ||||
| -rw-r--r-- | riscv/triggers.h | 6 |
3 files changed, 8 insertions, 8 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 9262199..0b271c7 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -1135,7 +1135,7 @@ void processor_t::trigger_updated(const std::vector<triggers::trigger_t *> &trig mmu->check_triggers_store = false; for (auto trigger : triggers) { - if (trigger->execute()) { + if (trigger->get_execute()) { mmu->check_triggers_fetch = true; } if (trigger->load()) { diff --git a/riscv/triggers.cc b/riscv/triggers.cc index 7c71199..10a50df 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -32,7 +32,7 @@ reg_t mcontrol_t::tdata1_read(const processor_t * const proc) const noexcept { v = set_field(v, MCONTROL_M, m); v = set_field(v, MCONTROL_S, s); v = set_field(v, MCONTROL_U, u); - v = set_field(v, MCONTROL_EXECUTE, execute_bit); + v = set_field(v, MCONTROL_EXECUTE, execute); v = set_field(v, MCONTROL_STORE, store_bit); v = set_field(v, MCONTROL_LOAD, load_bit); return v; @@ -66,11 +66,11 @@ bool mcontrol_t::tdata1_write(processor_t * const proc, const reg_t val) noexcep m = get_field(val, MCONTROL_M); s = get_field(val, MCONTROL_S); u = get_field(val, MCONTROL_U); - execute_bit = get_field(val, MCONTROL_EXECUTE); + execute = get_field(val, MCONTROL_EXECUTE); store_bit = get_field(val, MCONTROL_STORE); load_bit = get_field(val, MCONTROL_LOAD); // Assume we're here because of csrw. - if (execute_bit) + if (execute) timing = 0; return true; } @@ -104,7 +104,7 @@ bool mcontrol_t::simple_match(unsigned xlen, reg_t value) const { match_result_t mcontrol_t::memory_access_match(processor_t * const proc, operation_t operation, reg_t address, std::optional<reg_t> data) { state_t * const state = proc->get_state(); - if ((operation == triggers::OPERATION_EXECUTE && !execute_bit) || + if ((operation == triggers::OPERATION_EXECUTE && !execute) || (operation == triggers::OPERATION_STORE && !store_bit) || (operation == triggers::OPERATION_LOAD && !load_bit) || (state->prv == PRV_M && !m) || diff --git a/riscv/triggers.h b/riscv/triggers.h index 7d0f0ac..768d9c9 100644 --- a/riscv/triggers.h +++ b/riscv/triggers.h @@ -51,7 +51,7 @@ public: virtual bool tdata2_write(processor_t * const proc, const reg_t val) noexcept = 0; virtual bool chain() const { return false; } - virtual bool execute() const { return false; } + virtual bool get_execute() const { return false; } virtual bool store() const { return false; } virtual bool load() const { return false; } @@ -90,7 +90,7 @@ public: virtual bool tdata1_write(processor_t * const proc, const reg_t val) noexcept override; virtual bool chain() const override { return chain_bit; } - virtual bool execute() const override { return execute_bit; } + virtual bool get_execute() const override { return execute; } virtual bool store() const override { return store_bit; } virtual bool load() const override { return load_bit; } @@ -108,7 +108,7 @@ public: bool m = false; bool s = false; bool u = false; - bool execute_bit = false; + bool execute = false; bool store_bit = false; bool load_bit = false; }; |