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| author | YenHaoChen <39526191+YenHaoChen@users.noreply.github.com> | 2022-10-26 08:26:50 +0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-11-15 10:49:09 -0800 |
| commit | 07e3d415c5c28d505882fe81f568d6d278520ee5 (patch) | |
| tree | 526844e421a78b23ec08d66709a4a6c37fd94599 | |
| parent | 8a4ba87d3af07830ea48dafda7e11d873811d444 (diff) | |
| download | riscv-isa-sim-07e3d415c5c28d505882fe81f568d6d278520ee5.zip riscv-isa-sim-07e3d415c5c28d505882fe81f568d6d278520ee5.tar.gz riscv-isa-sim-07e3d415c5c28d505882fe81f568d6d278520ee5.tar.bz2 | |
Update riscv/triggers.cc
Co-authored-by: Tim Newsome <tim@sifive.com>
Signed-off-by: YenHaoChen <39526191+YenHaoChen@users.noreply.github.com>
| -rw-r--r-- | riscv/triggers.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/triggers.cc b/riscv/triggers.cc index b6fa4da..1e3c2bb 100644 --- a/riscv/triggers.cc +++ b/riscv/triggers.cc @@ -181,7 +181,7 @@ bool itrigger_t::tdata1_write(processor_t * const proc, const reg_t val) noexcep s = proc->extension_enabled('S') ? get_field(val, CSR_ITRIGGER_S) : 0; u = proc->extension_enabled('U') ? get_field(val, CSR_ITRIGGER_U) : 0; action = (action_t)get_field(val, CSR_ITRIGGER_ACTION); - if (action > 4 || (action==1 && dmode==0)) + if (action > 4 || (action==ACTION_DEBUG_MODE && dmode==0)) action = ACTION_DEBUG_EXCEPTION; return true; } |