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| author | Brian Campbell <Brian.Campbell@ed.ac.uk> | 2016-12-20 12:32:51 +0000 |
|---|---|---|
| committer | Brian Campbell <Brian.Campbell@ed.ac.uk> | 2016-12-21 11:37:37 +0000 |
| commit | 71f64bfe4eb2d4d1b0795b71db555fd825593ab3 (patch) | |
| tree | 3a2a7affffc642c4c0561fe87dd5cd98b3b7309a | |
| parent | 9e3b7bdc5ab045e2a526bbbbbb26475b6ef91468 (diff) | |
| download | riscv-isa-sim-71f64bfe4eb2d4d1b0795b71db555fd825593ab3.zip riscv-isa-sim-71f64bfe4eb2d4d1b0795b71db555fd825593ab3.tar.gz riscv-isa-sim-71f64bfe4eb2d4d1b0795b71db555fd825593ab3.tar.bz2 | |
Remove extra gdb protocol responses on register writes
| -rw-r--r-- | riscv/gdbserver.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc index c4e0fef..920cb8f 100644 --- a/riscv/gdbserver.cc +++ b/riscv/gdbserver.cc @@ -1820,8 +1820,6 @@ void gdbserver_t::handle_register_write(const std::vector<uint8_t> &packet) processor_t *p = sim->get_core(0); add_operation(new register_write_op_t(*this, n, value)); - - return send_packet("OK"); } void gdbserver_t::handle_memory_read(const std::vector<uint8_t> &packet) |