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| author | Jakub Palider <jpalider@marvell.com> | 2023-04-04 10:02:51 +0200 |
|---|---|---|
| committer | Jakub Palider <jpalider@marvell.com> | 2023-04-04 10:02:51 +0200 |
| commit | 96c64bce53ea3d8fa0344498b5512e5e2afd22bb (patch) | |
| tree | 5a285e1cf7f1638cdd8f3a1bc7d2945e700d8b24 | |
| parent | 929ff56a09462978628c59c22fe6cb6895aa136f (diff) | |
| download | riscv-isa-sim-96c64bce53ea3d8fa0344498b5512e5e2afd22bb.zip riscv-isa-sim-96c64bce53ea3d8fa0344498b5512e5e2afd22bb.tar.gz riscv-isa-sim-96c64bce53ea3d8fa0344498b5512e5e2afd22bb.tar.bz2 | |
Print cache stats even when no access
The cache stats are printed regardless on accesses they
recorded. This allows better insight into system operation
and provides consistent output for scripting.
Signed-off-by: Jakub Palider <jpalider@marvell.com>
| -rw-r--r-- | riscv/cachesim.cc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/riscv/cachesim.cc b/riscv/cachesim.cc index 498d407..24e87d3 100644 --- a/riscv/cachesim.cc +++ b/riscv/cachesim.cc @@ -76,9 +76,6 @@ cache_sim_t::~cache_sim_t() void cache_sim_t::print_stats() { - if (read_accesses + write_accesses == 0) - return; - float mr = 100.0f*(read_misses+write_misses)/(read_accesses+write_accesses); std::cout << std::setprecision(3) << std::fixed; |