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| author | Scott Johnson <scott.johnson@arilinc.com> | 2023-02-27 05:30:31 -0800 |
|---|---|---|
| committer | Scott Johnson <scott.johnson@arilinc.com> | 2023-04-04 09:21:39 -0700 |
| commit | 805d71705c28cd0404bba38032e4c7264b744bc7 (patch) | |
| tree | 824755949c7cf2832952ac8bb0dce827dde7577b | |
| parent | e4325fda2776e065400a791accb083a76db6f511 (diff) | |
| download | riscv-isa-sim-805d71705c28cd0404bba38032e4c7264b744bc7.zip riscv-isa-sim-805d71705c28cd0404bba38032e4c7264b744bc7.tar.gz riscv-isa-sim-805d71705c28cd0404bba38032e4c7264b744bc7.tar.bz2 | |
Don't waste time checking icount when unnecessary
| -rw-r--r-- | riscv/execute.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/execute.cc b/riscv/execute.cc index f412a35..acf0e90 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -263,7 +263,7 @@ void processor_t::step(size_t n) state.single_step = state.STEP_STEPPED; } - if (!state.serialized) { + if (!state.serialized && check_triggers_icount) { auto match = TM.detect_icount_match(); if (match.has_value()) { assert(match->timing == triggers::TIMING_BEFORE); |