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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-14 22:51:19 +0800 |
|---|---|---|
| committer | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-04-14 23:27:04 +0800 |
| commit | 107ee46f29f0a531a7542bc48537cfd0d565c067 (patch) | |
| tree | 5bbdfb649c1b5e24ef246dc355ecd7b5f03c10d8 | |
| parent | 97e9f7caaad9f468078206fcc9b30b3884c348cb (diff) | |
| download | riscv-isa-sim-107ee46f29f0a531a7542bc48537cfd0d565c067.zip riscv-isa-sim-107ee46f29f0a531a7542bc48537cfd0d565c067.tar.gz riscv-isa-sim-107ee46f29f0a531a7542bc48537cfd0d565c067.tar.bz2 | |
Add dsasm support for BF16 extensions
| -rw-r--r-- | disasm/disasm.cc | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/disasm/disasm.cc b/disasm/disasm.cc index fef9fac..9f2da34 100644 --- a/disasm/disasm.cc +++ b/disasm/disasm.cc @@ -1239,6 +1239,15 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) DEFINE_FX2TYPE(fle_q); } + if (isa->extension_enabled(EXT_ZFBFMIN)) { + DEFINE_FLOAD(flh) + DEFINE_FSTORE(fsh) + DEFINE_FR1TYPE(fcvt_bf16_s); + DEFINE_FR1TYPE(fcvt_s_bf16); + DEFINE_XFTYPE(fmv_h_x); + DEFINE_FXTYPE(fmv_x_h); + } + // ext-h if (isa->extension_enabled('H')) { DEFINE_XLOAD_BASE(hlv_b) @@ -1787,6 +1796,20 @@ void disassembler_t::add_instructions(const isa_parser_t* isa) } } + if (isa->extension_enabled(EXT_ZVFBFMIN)) { + DEFINE_FLOAD(flh) + DEFINE_FSTORE(fsh) + DEFINE_VECTOR_V(vfncvtbf16_f_f_w); + DEFINE_VECTOR_V(vfwcvtbf16_f_f_v); + DEFINE_XFTYPE(fmv_h_x); + DEFINE_FXTYPE(fmv_x_h); + } + + if (isa->extension_enabled(EXT_ZVFBFWMA)) { + DEFINE_VECTOR_VV(vfwmaccbf16_vv); + DEFINE_VECTOR_VF(vfwmaccbf16_vf); + } + #define DEFINE_PI3TYPE(code) add_pitype3_insn(this, #code, match_##code, mask_##code); #define DEFINE_PI4TYPE(code) add_pitype4_insn(this, #code, match_##code, mask_##code); #define DEFINE_PI5TYPE(code) add_pitype5_insn(this, #code, match_##code, mask_##code); |