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| author | Andrew Waterman <andrew@sifive.com> | 2023-04-11 17:47:10 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-04-11 17:47:10 -0700 |
| commit | 0b52bb625556477865b2a77f47ae3ceacbc2cd5c (patch) | |
| tree | c9cd8ea95ce0fbf5d0f760cd0b697f4ad0c6533f | |
| parent | eb75ab37a17ff4f8597b7b40283a08c38d2a6ff6 (diff) | |
| parent | 0b266f2a51ec8e6107c099b8af4a89c0b0bb125a (diff) | |
| download | riscv-isa-sim-0b52bb625556477865b2a77f47ae3ceacbc2cd5c.zip riscv-isa-sim-0b52bb625556477865b2a77f47ae3ceacbc2cd5c.tar.gz riscv-isa-sim-0b52bb625556477865b2a77f47ae3ceacbc2cd5c.tar.bz2 | |
Merge pull request #1311 from YenHaoChen/pr-show-d-mode
explicitly show D(-mode) instead of M(-mode) when in debug mode
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index c757d42..330bd30 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -722,6 +722,8 @@ void processor_t::set_privilege(reg_t prv) const char* processor_t::get_privilege_string() { + if (state.debug_mode) + return "D"; if (state.v) { switch (state.prv) { case 0x0: return "VU"; |