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| author | Andrew Waterman <andrew@sifive.com> | 2023-04-04 13:02:18 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-04-04 13:02:18 -0700 |
| commit | 09f29dbc54b61bb1130d3944726346e042cd2009 (patch) | |
| tree | 1ba62d73dda0069b6733fc52c4e7bf2959c2a83f | |
| parent | 035cc8e98d3e67fda5f2b2bfbec21b68630e99d7 (diff) | |
| parent | 3dd48fd91cd7c40e4d7daafa3991c5f2600cc9dd (diff) | |
| download | riscv-isa-sim-09f29dbc54b61bb1130d3944726346e042cd2009.zip riscv-isa-sim-09f29dbc54b61bb1130d3944726346e042cd2009.tar.gz riscv-isa-sim-09f29dbc54b61bb1130d3944726346e042cd2009.tar.bz2 | |
Merge pull request #1305 from Jakub-Palider/master-cache-stats
Add cache statistics print on demand
| -rw-r--r-- | riscv/cachesim.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/cachesim.h b/riscv/cachesim.h index d7046f9..7271954 100644 --- a/riscv/cachesim.h +++ b/riscv/cachesim.h @@ -100,6 +100,10 @@ class cache_memtracer_t : public memtracer_t { cache->set_log(log); } + void print_stats() + { + cache->print_stats(); + } protected: cache_sim_t* cache; |