diff options
author | Jerry Zhao <jerryz123@berkeley.edu> | 2024-06-20 14:24:51 -0700 |
---|---|---|
committer | Jerry Zhao <jerryz123@berkeley.edu> | 2024-06-21 10:29:20 -0700 |
commit | 9f5df7f4dbef18c8c22d5e9a8bfca48fc50cfdc6 (patch) | |
tree | 602032577d3c0df0a82078897b611cb447b61b6e | |
parent | 9ee100f580178c315c2d48cd712feda47a755248 (diff) | |
download | riscv-isa-sim-9f5df7f4dbef18c8c22d5e9a8bfca48fc50cfdc6.zip riscv-isa-sim-9f5df7f4dbef18c8c22d5e9a8bfca48fc50cfdc6.tar.gz riscv-isa-sim-9f5df7f4dbef18c8c22d5e9a8bfca48fc50cfdc6.tar.bz2 |
Disallow any vector, not just V, when no __int128 type is present
-rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index a813068..43f5627 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -44,7 +44,7 @@ processor_t::processor_t(const isa_parser_t *isa, const cfg_t *cfg, TM.proc = this; #ifndef HAVE_INT128 - if (isa->extension_enabled('V')) { + if (isa->has_any_vector()) { fprintf(stderr, "V extension is not supported on platforms without __int128 type\n"); abort(); } |