riscv/insns/vfncvt_rod_f_f_w.h


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// vfncvt.rod.f.f.v vd, vs2, vm
VI_VFP_CVT_SCALE
({
  require(0);
},
{
  softfloat_roundingMode = softfloat_round_odd;
  auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
  P.VU.elt<float16_t>(rd_num, i, true) = f32_to_f16(vs2);
},
{
  softfloat_roundingMode = softfloat_round_odd;
  auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
  P.VU.elt<float32_t>(rd_num, i, true) = f64_to_f32(vs2);
}, false)