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rocket-tools/riscv-gnu-toolchain/spike.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
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riscv
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processor.cc
Age
Commit message (
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Author
Files
Lines
2020-09-20
Don't throw virtual instruction exceptions for unimplemented CSRs
Andrew Waterman
1
-94
/
+124
2020-09-15
Populate tval registers on illegal-/virtual-instruction traps
Andrew Waterman
1
-7
/
+12
2020-09-15
No need to catch illegal CSRs in set_csr
Andrew Waterman
1
-16
/
+2
2020-09-11
Add MIP_MEIP to all_ints (#543)
Abhinay Kayastha
1
-1
/
+1
2020-09-01
Fix MIDELEG and MEDELEG emulation when H-extension is available (#537)
Anup Patel
1
-0
/
+7
2020-08-31
rvv: reading vcsr needs to enable mstatus.vs
Chih-Min Chao
1
-0
/
+1
2020-08-27
rf: remove bit extraction from processor.h
Chih-Min Chao
1
-5
/
+6
2020-08-27
rvv: remove quad instructions
Chih-Min Chao
1
-5
/
+0
2020-08-12
mcounteren does not exist if U-mode is not implemented
Andrew Waterman
1
-1
/
+4
2020-08-03
rvv: add 'vstartalu" option to --varch arugment
Chih-Min Chao
1
-0
/
+4
2020-07-29
rvv: remove isa string zvamoand zvlsseg
Chih-Min Chao
1
-11
/
+0
2020-07-29
rvv: remove veew/vemul state
Chih-Min Chao
1
-2
/
+0
2020-07-29
rvv: remove slen
Chih-Min Chao
1
-6
/
+3
2020-07-29
rvv: initialize vector register as zero
Chih-Min Chao
1
-1
/
+2
2020-07-28
Incorporate RVV 1.0 vtype layout change
Andrew Waterman
1
-3
/
+2
2020-07-16
Fix legalize_privilege for extension H (#508)
Abhinay Kayastha
1
-1
/
+1
2020-07-09
Merge pull request #493 from avpatel/riscv-hyp-ext-v0.6.1
Andrew Waterman
1
-43
/
+438
2020-07-09
Implement hypervisor CSRs read/write
Anup Patel
1
-43
/
+438
2020-07-08
rvv: vstart register needs only lg2(VLEN) bits (#501)
Chih-Min Chao
1
-1
/
+1
2020-07-06
If n_pmp=0, then pmp is not implemented hence raise trap
Abhinay Kayastha
1
-0
/
+3
2020-07-02
commitlog: support csr access
Chih-Min Chao
1
-1
/
+94
2020-06-16
ext: handle diaseembler initialization from --extension
Chih-Min Chao
1
-0
/
+4
2020-06-10
ext: support default library name and fix isa parser
Chih-Min Chao
1
-3
/
+7
2020-05-28
rvv: use zvqmac to enable vector qmac
Chih-Min Chao
1
-0
/
+5
2020-05-28
rvv: apply new overlapping and align macro
Chih-Min Chao
1
-1
/
+0
2020-05-28
rvv: add new explicit eew load/store instructions
Chih-Min Chao
1
-0
/
+5
2020-05-28
rvv: add amo instructions
Chih-Min Chao
1
-0
/
+6
2020-05-28
rvv: extenc VU structure to support 0.9 new fields
Chih-Min Chao
1
-6
/
+17
2020-05-26
Report haltgroup halt cause, per the debug spec. (#473)
Tim Newsome
1
-1
/
+1
2020-05-20
Make sure VLEN/ELEN/SLEN are initialized even without V extension
Andrew Waterman
1
-2
/
+1
2020-05-19
Fix state.misa garbage initialization
Udit Khanna
1
-1
/
+1
2020-05-12
Hardwire mstatus.[sie,spie] to zero if 'S' mode absent
Udit Khanna
1
-3
/
+2
2020-05-10
Merge branch 'configurable_PMP'
Andrew Waterman
1
-14
/
+53
2020-05-10
Implement CSR read/write behavior for coarse-grain PMP
Andrew Waterman
1
-2
/
+9
2020-05-10
Implement configurable PMP count
Andrew Waterman
1
-6
/
+16
2020-05-09
Support consuming PMP number and granularity from DTB
Andrew Waterman
1
-0
/
+22
2020-05-09
Rename n_pmp constant to max_pmp
Andrew Waterman
1
-7
/
+7
2020-05-04
parser: fp16: require F extension
Chih-Min Chao
1
-0
/
+3
2020-04-24
parser: exhance --isa to support extended extension
Chih-Min Chao
1
-24
/
+62
2020-04-20
rvv: fix vcsr related status change
Chih-Min Chao
1
-4
/
+14
2020-04-20
Move vxrm/vxsat from fcsr to vcsr
Andrew Waterman
1
-12
/
+10
2020-04-09
op: update CSR
Chih-Min Chao
1
-4
/
+4
2020-04-02
option: flag x extension without loading shared lib (#439)
Chih-Min Chao
1
-1
/
+5
2020-04-02
Deny hart access to debug CSRs when not in D-mode
Andrew Waterman
1
-0
/
+8
2020-03-27
Merge pull request #433 from chihminchao/rvv-fix-2020-03-27
Andrew Waterman
1
-0
/
+2
2020-03-27
Write execution logs to a named log file (#409)
Rupert Swarbrick
1
-16
/
+12
2020-03-27
rvv: check vlen == slen
Chih-Min Chao
1
-0
/
+2
2020-03-23
rvv: fix WARL behavior for vxsat and vxrm
Chih-Min Chao
1
-2
/
+2
2020-03-09
rvv: enhance --varch to parse string type options
Zhen Wei
1
-30
/
+42
2020-03-04
Don't clobber trigger types when initializing state
Andrew Waterman
1
-1
/
+1
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