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AgeCommit message (Expand)AuthorFilesLines
2020-09-20Don't throw virtual instruction exceptions for unimplemented CSRsAndrew Waterman1-94/+124
2020-09-15Populate tval registers on illegal-/virtual-instruction trapsAndrew Waterman1-7/+12
2020-09-15No need to catch illegal CSRs in set_csrAndrew Waterman1-16/+2
2020-09-11Add MIP_MEIP to all_ints (#543)Abhinay Kayastha1-1/+1
2020-09-01Fix MIDELEG and MEDELEG emulation when H-extension is available (#537)Anup Patel1-0/+7
2020-08-31rvv: reading vcsr needs to enable mstatus.vsChih-Min Chao1-0/+1
2020-08-27rf: remove bit extraction from processor.hChih-Min Chao1-5/+6
2020-08-27rvv: remove quad instructionsChih-Min Chao1-5/+0
2020-08-12mcounteren does not exist if U-mode is not implementedAndrew Waterman1-1/+4
2020-08-03rvv: add 'vstartalu" option to --varch arugmentChih-Min Chao1-0/+4
2020-07-29rvv: remove isa string zvamoand zvlssegChih-Min Chao1-11/+0
2020-07-29rvv: remove veew/vemul stateChih-Min Chao1-2/+0
2020-07-29rvv: remove slenChih-Min Chao1-6/+3
2020-07-29rvv: initialize vector register as zeroChih-Min Chao1-1/+2
2020-07-28Incorporate RVV 1.0 vtype layout changeAndrew Waterman1-3/+2
2020-07-16Fix legalize_privilege for extension H (#508)Abhinay Kayastha1-1/+1
2020-07-09Merge pull request #493 from avpatel/riscv-hyp-ext-v0.6.1Andrew Waterman1-43/+438
2020-07-09Implement hypervisor CSRs read/writeAnup Patel1-43/+438
2020-07-08rvv: vstart register needs only lg2(VLEN) bits (#501)Chih-Min Chao1-1/+1
2020-07-06If n_pmp=0, then pmp is not implemented hence raise trapAbhinay Kayastha1-0/+3
2020-07-02commitlog: support csr accessChih-Min Chao1-1/+94
2020-06-16ext: handle diaseembler initialization from --extensionChih-Min Chao1-0/+4
2020-06-10ext: support default library name and fix isa parserChih-Min Chao1-3/+7
2020-05-28rvv: use zvqmac to enable vector qmacChih-Min Chao1-0/+5
2020-05-28rvv: apply new overlapping and align macroChih-Min Chao1-1/+0
2020-05-28rvv: add new explicit eew load/store instructionsChih-Min Chao1-0/+5
2020-05-28rvv: add amo instructionsChih-Min Chao1-0/+6
2020-05-28rvv: extenc VU structure to support 0.9 new fieldsChih-Min Chao1-6/+17
2020-05-26Report haltgroup halt cause, per the debug spec. (#473)Tim Newsome1-1/+1
2020-05-20Make sure VLEN/ELEN/SLEN are initialized even without V extensionAndrew Waterman1-2/+1
2020-05-19Fix state.misa garbage initializationUdit Khanna1-1/+1
2020-05-12Hardwire mstatus.[sie,spie] to zero if 'S' mode absentUdit Khanna1-3/+2
2020-05-10Merge branch 'configurable_PMP'Andrew Waterman1-14/+53
2020-05-10Implement CSR read/write behavior for coarse-grain PMPAndrew Waterman1-2/+9
2020-05-10Implement configurable PMP countAndrew Waterman1-6/+16
2020-05-09Support consuming PMP number and granularity from DTBAndrew Waterman1-0/+22
2020-05-09Rename n_pmp constant to max_pmpAndrew Waterman1-7/+7
2020-05-04parser: fp16: require F extensionChih-Min Chao1-0/+3
2020-04-24parser: exhance --isa to support extended extensionChih-Min Chao1-24/+62
2020-04-20rvv: fix vcsr related status changeChih-Min Chao1-4/+14
2020-04-20Move vxrm/vxsat from fcsr to vcsrAndrew Waterman1-12/+10
2020-04-09op: update CSRChih-Min Chao1-4/+4
2020-04-02option: flag x extension without loading shared lib (#439)Chih-Min Chao1-1/+5
2020-04-02Deny hart access to debug CSRs when not in D-modeAndrew Waterman1-0/+8
2020-03-27Merge pull request #433 from chihminchao/rvv-fix-2020-03-27Andrew Waterman1-0/+2
2020-03-27Write execution logs to a named log file (#409)Rupert Swarbrick1-16/+12
2020-03-27rvv: check vlen == slenChih-Min Chao1-0/+2
2020-03-23rvv: fix WARL behavior for vxsat and vxrmChih-Min Chao1-2/+2
2020-03-09rvv: enhance --varch to parse string type optionsZhen Wei1-30/+42
2020-03-04Don't clobber trigger types when initializing stateAndrew Waterman1-1/+1
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