aboutsummaryrefslogtreecommitdiff
path: root/riscv/insns
AgeCommit message (Expand)AuthorFilesLines
2020-07-29rvv: add vrgatherei16.vvChih-Min Chao1-0/+33
2020-07-29rvv: add new whole reg load/store instructionsChih-Min Chao21-17/+39
2020-07-29rvv: op: fix amo namingChih-Min Chao36-0/+0
2020-07-15commitlog: fix vmvnfr.v register information (#506)Chih-Min Chao1-4/+17
2020-07-13rvv: fix viota.m dst and src overlapping rule (#504)Chih-Min Chao1-5/+1
2020-07-09Implement new instructions of hypervisor extensionAnup Patel15-0/+63
2020-07-09Implement hypervisor CSRs read/writeAnup Patel4-4/+19
2020-07-08Extend trap classes to pass more informationAnup Patel2-2/+2
2020-07-02rvv: make vmvfnr respect vstartChih-Min Chao1-5/+4
2020-06-25rvv: fix viota.m overlapping ruleChih-Min Chao1-1/+5
2020-06-17rvv: make v[sl]1r respect vstartChih-Min Chao2-2/+2
2020-06-16zfh: implement all instructionsChih-Min Chao36-0/+167
2020-06-15remove the redundant code (#488)Dave Wen1-1/+1
2020-06-11rvv: fix some style and dead codeChih-Min Chao3-12/+2
2020-06-08Fix priority of misaligned exceptions for store-conditionalAndrew Waterman2-4/+10
2020-06-04rvv: fix vfmv.s.f for non NaN-boxed caseChih-Min Chao1-8/+2
2020-06-04rvv: commitlog: fix vfslideChih-Min Chao2-2/+2
2020-06-04rvv: fix vms[oib]f.m overlapping ruleChih-Min Chao3-7/+7
2020-05-28rvv: apply new overlapping and align macroChih-Min Chao12-32/+30
2020-05-28rvv: add e8 type for narrow/widen conversionChih-Min Chao15-0/+51
2020-05-28rvv: add new explicit eew load/store instructionsChih-Min Chao76-217/+65
2020-05-28rvv: add amo instructionsChih-Min Chao36-0/+72
2020-05-28rvv: add new singed/unsiged extension instructionsChih-Min Chao6-0/+6
2020-05-28rvv: wrap align and overlap checking macroChih-Min Chao5-5/+5
2020-05-28rvv: remove vmlenChih-Min Chao15-38/+32
2020-05-28rvv: handle inactive and NaN case for vfredsumChih-Min Chao6-0/+6
2020-05-04rvv: fp16: support element movement instructionsChih-Min Chao6-15/+67
2020-05-04rvv: fp16: support vfwxxx.[wv][vf] instructionsChih-Min Chao18-0/+54
2020-05-04rvv: fp16: support conversion instrucitonsChih-Min Chao21-126/+124
2020-05-04rvv: fp16: support reduction instructionsChih-Min Chao6-6/+18
2020-05-04rvv: fp16: support comparison instructionsChih-Min Chao10-0/+30
2020-05-04rvv: fp16: support .vf instructionsChih-Min Chao24-2/+80
2020-05-04rvv: fp16: support .vv instructionsChih-Min Chao21-0/+63
2020-05-04rvv: remove unused WIDE_END loop macroChih-Min Chao7-7/+7
2020-04-28Merge pull request #456 from chihminchao/rvv-fix-2020-04-28Andrew Waterman2-2/+2
2020-04-28rvv: commitlog: fix vmsgtu.vi and vmsleu.vi dst informationChih-Min Chao2-2/+2
2020-04-28Fix vnclip.wi bugAndrew Waterman1-1/+1
2020-04-24rvv: leave only SEW-bit segment storeChih-Min Chao16-151/+51
2020-04-24rvv: leave only SEW-bit segment loadChih-Min Chao28-65/+64
2020-04-24rvv: add vfslide1[down|up].vf and refine checking ruleChih-Min Chao8-35/+70
2020-04-20rvv: add float conversion for rtz variantsChih-Min Chao6-0/+56
2020-04-09rvv: vslide[1]up now allows mask overlap when LMUL=1Chih-Min Chao3-3/+3
2020-03-27rvv: fix int_max/min value calculationChih-Min Chao8-23/+26
2020-03-27rvv: fix vssra.vi e64 corner caseChih-Min Chao1-1/+1
2020-03-27rvv: fix vmv reg checking failureChih-Min Chao3-1/+6
2020-03-23rvv: restrict segment load register ruleChih-Min Chao3-0/+3
2020-03-23rvv: fix vdiv corner caseChih-Min Chao2-2/+2
2020-03-23Don't acquire load reservation in the event of a faultAndrew Waterman2-2/+4
2020-03-20ebreak should write mtval with 0, not pcAndrew Waterman2-2/+2
2020-03-12rvv: commitlog: fix vrgather_vv dump (#421)Chih-Min Chao1-4/+4
generated by cgit v1.1 at 2024-07-11 16:20:52 +0000