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AgeCommit message (Expand)AuthorFilesLines
2020-07-31test_hetero_mcheterogeneous_mcUdit Khanna1-1/+3
2020-07-29f16: fix Nan-Box macroChih-Min Chao1-1/+1
2020-07-29rvv: fix frac_lmul get functionChih-Min Chao1-1/+1
2020-07-29rvv: remove isa string zvamoand zvlssegChih-Min Chao3-18/+0
2020-07-29rvv: remove veew/vemul stateChih-Min Chao3-32/+25
2020-07-29rvv: add vrgatherei16.vvChih-Min Chao3-0/+37
2020-07-29rvv: add new whole reg load/store instructionsChih-Min Chao24-21/+187
2020-07-29rvv: op: rearrange some instruction since generation order changeChih-Min Chao1-36/+36
2020-07-29rvv: op: fix amo namingChih-Min Chao38-144/+144
2020-07-29rvv: remove slenChih-Min Chao2-8/+5
2020-07-29rvv: initialize vector register as zeroChih-Min Chao1-1/+2
2020-07-28Incorporate RVV 1.0 vtype layout changeAndrew Waterman2-5/+4
2020-07-16Fix legalize_privilege for extension H (#508)Abhinay Kayastha1-1/+1
2020-07-15commitlog: fix vmvnfr.v register information (#506)Chih-Min Chao1-4/+17
2020-07-13rvv: fix viota.m dst and src overlapping rule (#504)Chih-Min Chao1-5/+1
2020-07-09Merge pull request #493 from avpatel/riscv-hyp-ext-v0.6.1Andrew Waterman34-145/+924
2020-07-09Add bootargs command-line option to SpikeAnup Patel4-7/+21
2020-07-09Implement new instructions of hypervisor extensionAnup Patel16-0/+81
2020-07-09Implement hypervisor two-stage MMUAnup Patel2-51/+179
2020-07-09Implement hypervisor CSRs read/writeAnup Patel8-53/+502
2020-07-08rvv: vstart register needs only lg2(VLEN) bits (#501)Chih-Min Chao1-1/+1
2020-07-08Extend trap classes to pass more informationAnup Patel7-28/+60
2020-07-08Add hypervisor extension related CSR and instruction definesAnup Patel1-6/+81
2020-07-06If n_pmp=0, then pmp is not implemented hence raise trapAbhinay Kayastha1-0/+3
2020-07-02commitlog: support csr accessChih-Min Chao2-2/+99
2020-07-02commitlog: simplify print_value pathChih-Min Chao1-26/+27
2020-07-02commitlog: extend hint bit to record csr accessChih-Min Chao3-6/+12
2020-07-02rvv: make vmvfnr respect vstartChih-Min Chao1-5/+4
2020-06-25rvv: remove unecessary accessChih-Min Chao1-3/+0
2020-06-25rvv: fix viota.m overlapping ruleChih-Min Chao1-1/+5
2020-06-17rvv: make v[sl]1r respect vstartChih-Min Chao2-2/+2
2020-06-17rvv: commitlog: fix fractional lmul dumpChih-Min Chao1-2/+2
2020-06-16Merge pull request #490 from chihminchao/rvv-fix-2020-06-17Andrew Waterman2-0/+10
2020-06-16zfh: support register dump in interactive modeChih-Min Chao2-0/+10
2020-06-16ext: handle diaseembler initialization from --extensionChih-Min Chao1-0/+4
2020-06-16zfh: implement all instructionsChih-Min Chao37-1/+207
2020-06-16zfh: op: add scalar opcodeChih-Min Chao1-0/+108
2020-06-15remove the redundant code (#488)Dave Wen2-2/+1
2020-06-11rvv: fix index and amo overlapping ruleChih-Min Chao1-4/+23
2020-06-11rvv: add widen overlapping helper and related widen ruleChih-Min Chao1-8/+52
2020-06-11rvv: fix comparison and narrow overlapping ruleChih-Min Chao1-3/+6
2020-06-11rvv: fix some style and dead codeChih-Min Chao3-12/+2
2020-06-10build: fix quota string parameterChih-Min Chao1-1/+1
2020-06-10Merge pull request #485 from chihminchao/custom-extAndrew Waterman3-8/+23
2020-06-10ext: build libriscv PIC to make it linkable to ext libraryChih-Min Chao1-0/+2
2020-06-10ext: support default library name and fix isa parserChih-Min Chao2-8/+21
2020-06-08Fix performance regressionAndrew Waterman1-1/+1
2020-06-08Fix priority of misaligned exceptions for store-conditionalAndrew Waterman3-5/+14
2020-06-04rvv: fix vfmv.s.f for non NaN-boxed caseChih-Min Chao1-8/+2
2020-06-04rvv: commitlog: fix vfslideChih-Min Chao2-2/+2
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