| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2020-05-28 | rvv: add new explicit eew load/store instructions | Chih-Min Chao | 1 | -13/+0 |
| 2020-04-24 | rvv: leave only SEW-bit segment store | Chih-Min Chao | 1 | -33/+11 |
| 2020-02-18 | Vector stores don't care if rd overlaps v0 (#400) | Andrew Waterman | 1 | -1/+1 |
| 2019-11-11 | rvv: add reg checking rule for ldst | Chih-Min Chao | 1 | -1/+2 |
| 2019-11-11 | rvv: remove configuable tail-zero | Chih-Min Chao | 1 | -13/+8 |
| 2019-07-19 | Check vtype.vill for all vector instructions except vsetvl[i] | Andrew Waterman | 1 | -0/+1 |
| 2019-06-18 | rvv: add load/store instructions | Chih-Min Chao | 1 | -0/+38 |
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index : rocket-tools/riscv-gnu-toolchain/spike.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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