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path: root/riscv/insns/vcompress_vm.h
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2024-08-01vcompress.vm: Check if there is any vector extension before using vector CSRsYenHaoChen1-4/+5
2024-03-11Update vcompress.vm to not write vstart with 0 upon completionrbuchner1-1/+1
Vmcompress.vm requires vstart==0, so writing vstart with 0 is redundant. To do this, spin off VI_LOOP_END_BASE from VI_LOOP_END. VI_LOOP_END will contain VI_LOOP_END_BASE as well as a write of 0 to vstart. See #1623 for full discussion.
2021-09-29Convert vstart to csr_tScott Johnson1-1/+1
Adds commit log events for vstart to many vector instructions.
2020-05-28rvv: apply new overlapping and align macroChih-Min Chao1-3/+3
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-05-28rvv: remove vmlenChih-Min Chao1-3/+2
vmlen has be changed to 1 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-01-22commitlog: rvv: add commitlog support to misc instrutionsChih-Min Chao1-4/+4
other instructions, which doesn't use macro in decoder.h Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: add reg checking for specifial instructionsChih-Min Chao1-15/+8
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-11rvv: remove configuable tail-zeroChih-Min Chao1-1/+1
tail zero feature has been removed after v0.8-draft Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-07-19Check vtype.vill for all vector instructions except vsetvl[i]Andrew Waterman1-1/+1
2019-06-18rvv: add integer/fixed-point/mask/reduction/permutation instructionsChih-Min Chao1-0/+41
based on v-spec 0.7.1, support sections: 12/13/15.1 ~ 15.2/16/17 element size: 8/16/32/64 support ediv: 1 Signed-off-by: Bruce Hoult <bruce@hoult.org> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Dave Wen <dave.wen@sifive.com>
generated by cgit v1.1 at 2024-09-12 04:25:42 +0000