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This change allows to create custom implementations of `abstract_mem_t`
and inject them when constructing `sim_t`. The current `mem_t`
implementation remains unchanged.
Fixes #1408.
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Plugins should now implement and register a device_factory_t to
configure how that device should be parsed from a FDT, and an optional
default DTS string.
This drops support for command-line flag-based device configuration
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In keeping with the spirit of simif_t.
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This is a large delta because the old implementation baked in multiple
assumptions about the contiguity of hart IDs.
As a side effect, fix implementation for big-endian hosts.
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This commit started as an attempt to make the PLIC tolerant of
discontiguous hart IDs, but it turns out it was already most of
the way there: PLIC contexts can still be dense even if the hart
IDs are not.
Nevertheless, I wanted to avoid passing the procs vector directly to
the plic_t constructor. In removing it, I realized I could also get
rid of the smode parameter by querying whether each hart has S-mode.
This is also more correct; previously, we were instantiating the PLIC
as though all harts had S-mode, regardless of whether they actually did.
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On my Mac Mini, calling `poll()` on stdin takes around 10 us, and we
are invoking it every 20 us or so. Reduce the frequency of polling
by 16x when not actively receiving data, thereby reducing the fraction
of time spent in `poll()` to a trivial amount.
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The ns16550 is a widely use serial device so we add a simplified
ns16550 device emulation which is good enough for Linux, OpenSBI,
and hypervisors to use as console.
Signed-off-by: Anup Patel <anup@brainfault.org>
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We need an interrupt controller in Spike which will allow us to
emulate more real-world devices such as UART, VirtIO net, VirtIO
block, etc.
The RISC-V PLIC (or SiFive PLIC) is the commonly used interrupt
controller in existing RISC-V platforms so this patch adds PLIC
emulation for Spike.
Signed-off-by: Anup Patel <anup@brainfault.org>
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We add an abstract interrupt controller interface which can be used by
devices to trigger wired interrupts.
Signed-off-by: Anup Patel <anup@brainfault.org>
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Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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For some reason, the old accessors for the non-sparse version were left
dangling. These methods are used by the --kernel and --initrd options,
and so those options were just broken.
This also fixes a memory leak and refactors the implementation a bit.
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This patch splites the target-requested memory regions into pages and only
allocates host memory when it is accessed to reduce larget memory sceniaro
in 64 bit target system
Co-authored-by: Dave.Wen <dave.wen@sifive.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This patch adds optional support clint timer incrementing at
real-time rate. This can be enabled by passing command line
parameter "--real-time-clint".
This feature can be used for:
1. Checking whether any code addition to Spike is slowing down
simulation too much
2. Comparing run-time for software on Spike with other functional
simulators (such as QEMU)
Signed-off-by: Anup Patel <anup.patel@wdc.com>
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* mem_t: Throw an error if zero-sized memory is requested
If for some reason the user requests a memory size of 0 megabytes, print
a useful error message.
* Check for overflow in memory size
If the user passes in a large enough memory size (-m) that the size in
bytes doesn't fit into size_t, catch this error in the make_mems function.
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- https://github.com/riscv/riscv-tools/issues/69
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Debug exception -> ROM -> RAM -> ROM, then something goes wrong.
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This should replace the ROM hack I implemented earlier, but for now both
exist together.
Back to the point where gdb connects, core jumps to ROM->RAM->ROM.
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