Age | Commit message (Collapse) | Author | Files | Lines | |
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2024-04-18 | Add Zicfiss extension from CFI extension, v0.4.0 | SuHsien Ho | 1 | -0/+1 | |
1. Add EXT_ZICFISS for enable Zicfiss with zicfiss extension name. 2. Add new software exception with tval 3 for shadow stack. 3. Implement sspush_x1/sspush_x5/sspopchk_x1/sspopchk_x5/ssrdp/ssamoswap_w/ssamoswap_d. 4. Implement c_sspush_x1/c_sspopchk_x5 in c_lui.h which has same encoding. 5. Add new special access type ss_access in xlate_flags_t for checking special read/write permission in SS(Shadow Stack) page. 6. Add new ss_load/ss_store/ssamoswap to enable ss_access flag. 7. Check special pte(xwr=010) of SS page. | |||||
2023-10-18 | Revert "tmp" | Andrew Waterman | 1 | -1/+0 | |
This reverts commit 1de1e81952e387ef6b282dc46f0fdf9ae4f74df5. | |||||
2023-10-18 | tmp | Andrew Waterman | 1 | -0/+1 | |
2023-06-19 | Zvk: Implement Zvbb, Vector Bit-manipulation for Cryptography | Eric Gouriou | 1 | -0/+1 | |
Implement the proposed instructions in Zvbb: - vandn.{vv,vx}, vector bitwise and-not - vbrev.v, vector bit reverse in element - vbrev8.v, vector bit reverse in bytes - vrev8.v, vector byte reverse - vctz.v, vector count trailing zeros - vclz.v, vector count leading zeros - vcpop.v, vector population count - vrol.{vv,vx}, vector rotate left - vror.{vi,vv,vx}, vector rotate right - vwsll.{vi,vv,vx} vector widening shift left logical A new instruction field, 'zimm6', is introduced, encoded in bits [15, 19] and [26].. It is used by "vror.vi" to encode a shift immediate in [0, 63]. Co-authored-by: Raghav Gupta <rgupta@rivosinc.com> Co-authored-by: Stanislaw Kardach <kda@semihalf.com> Signed-off-by: Eric Gouriou <ego@rivosinc.com> | |||||
2023-05-26 | Use HAVE_INT128 instead of __SIZEOF_INT128__ | Gianluca Guida | 1 | -5/+0 | |
Make sure that the configure decision on 128-bit is consistent during compilation. Also move uint128_t definition. | |||||
2023-02-21 | Update fields name for sreg1/sreg2 | Weiwei Li | 1 | -2/+2 | |
2022-12-15 | Use relative include paths to support public usage of these headers | Jerry Zhao | 1 | -1/+1 | |
2022-12-15 | Split decode.h into public decode.h and private decode_macros.h | Jerry Zhao | 1 | -310/+2 | |
* decode.h contains constants/typedefs/classes. This should not depend on config.h * decode_macros.h contains internally used macros, and depends on config.h | |||||
2022-12-12 | Pull p/v_ext_macros.h out of decode.h | Jerry Zhao | 1 | -2/+0 | |
2022-12-05 | Merge pull request #1162 from riscv-software-src/sfence | Andrew Waterman | 1 | -1/+3 | |
SFENCE.W.INVAL and SFENCE.INVAL.IR should check privilege mode | |||||
2022-12-05 | SFENCE.INVAL.IR and SFENCE.W.INVAL are illegal in [V]U modes | Andrew Waterman | 1 | -0/+2 | |
See discussion on https://lists.riscv.org/g/tech-privileged/message/1213 | |||||
2022-12-04 | Make require_novirt macro an expression, not a statement | Andrew Waterman | 1 | -1/+1 | |
This improves composability by allowing its use in other expressions. | |||||
2022-11-28 | Fix type error in some platform | Weiwei Li | 1 | -1/+1 | |
2022-11-17 | add support for zcmt | Weiwei Li | 1 | -0/+2 | |
add suport for jvt: Table entries follow the current data endianness | |||||
2022-11-17 | add support for zcmp | Weiwei Li | 1 | -0/+75 | |
2022-11-17 | add support for zcb | Weiwei Li | 1 | -0/+3 | |
2022-10-04 | Fix ignored-qualifiers warnings in get_field/set_field macros | Andrew Waterman | 1 | -2/+6 | |
2022-10-04 | Rewrite READ_REG macro to avoid GNU statement expression extension | Andrew Waterman | 1 | -1/+1 | |
This way, it can be used as an expression within a template argument. | |||||
2022-09-08 | Remove unnecessary argument alu(always false) from macro | Weiwei Li | 1 | -3/+1 | |
require_vector_novtype | |||||
2022-08-10 | Add space between if/while/switch and '(' | Weiwei Li | 1 | -3/+3 | |
Add space between ')' and '{' | |||||
2022-08-04 | Add stateen related check for float point instructions | Weiwei Li | 1 | -1/+2 | |
2022-08-04 | Modify F/D/Zfh instructions to add support for Zfinx/Zdinx/Zhinx{min} ↵ | liweiwei | 1 | -0/+42 | |
instructions change the extention check for F/D/Zfh instructions modify the F/D/Zfh instructions to read X regs when enable Zfinx Co-authored-by: wangmeng <shusheng8495@hotmail.com> | |||||
2022-06-06 | Don't mask instruction bits | Andrew Waterman | 1 | -1/+1 | |
No longer needed, since they are no longer sign-extended. Fixes #1022 by eliminating undefined behavior (64-bit instructions resulted in a shift amount equal to the datatype width). | |||||
2022-06-06 | insn_t: don't rely on sign-extension of internal encoding | Andrew Waterman | 1 | -3/+3 | |
2022-06-03 | Remove nonstandard length encoding (#1023) | Andrew Waterman | 1 | -1/+0 | |
This was an artifact of an old P-extension draft that erroneously allocated a reserved major opcode. The newer draft uses a different opcode, so this hack is no longer needed. | |||||
2022-06-01 | Remove the now-unused PC_SERIALIZE_WFI | Kip Walker | 1 | -2/+0 | |
When WFI was changed to throw a C++ exception, the special-npc signaling became obsolete. | |||||
2022-05-05 | Factor out P extension macros into their own headerfactor-out-macros | Andrew Waterman | 1 | -500/+1 | |
No functional change. | |||||
2022-05-05 | Factor out V extension macros into their own header | Andrew Waterman | 1 | -2069/+1 | |
No functional change. | |||||
2022-04-14 | fix style problems in decode.h and processor.cc | Weiwei Li | 1 | -266/+266 | |
2022-04-09 | Replaced vector loop compare body with newly defined macro | 4vtomat | 1 | -90/+11 | |
This commit uses new macro to replace loop compare body to enhance code reuse. | |||||
2022-04-09 | Adding new macro to replace repetitive code | 4vtomat | 1 | -0/+15 | |
2022-02-23 | rvv: add missing elen checking for some ldst (#927) | Chih-Min Chao | 1 | -0/+2 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2022-01-30 | add instructions function for cmo | liweiwei | 1 | -0/+14 | |
prefetch.* are hints and share the encoding of ORI with rd = 0. so it can share the implementation of ORI and execute as no-ops | |||||
2022-01-25 | Add more assertion for fcvt (#910) | Yueh-Ting (eop) Chen | 1 | -0/+2 | |
2022-01-10 | Merge pull request #899 from riscv-software-src/rv32e | Andrew Waterman | 1 | -2/+4 | |
Add RV32E/RV64E base ISA support | |||||
2022-01-09 | Changes to be cleaner wrt. -Wextra | Andrew Waterman | 1 | -1/+1 | |
h/t @jerinjoy See #901 | |||||
2022-01-06 | Support RV32E/RV64E base ISAs | Andrew Waterman | 1 | -2/+4 | |
2021-12-27 | Fix check for fcvt (#897) | Yueh-Ting (eop) Chen | 1 | -9/+18 | |
2021-12-23 | Fix check for fcvt (#894) | Yueh-Ting (eop) Chen | 1 | -2/+2 | |
2021-12-21 | Add missing check for floating-point merge instructions (#893) | Yueh-Ting (eop) Chen | 1 | -4/+6 | |
2021-12-17 | Merge pull request #881 from eopXD/simplify-float-convert | Andrew Waterman | 1 | -30/+145 | |
Simplify float convert instructions | |||||
2021-12-12 | Fix minor type-o (#885) | Yueh-Ting (eop) Chen | 1 | -2/+2 | |
2021-12-09 | Simplify vfwcvt | eopXD | 1 | -39/+50 | |
2021-12-09 | Simplfy vfcvt | eopXD | 1 | -0/+34 | |
2021-12-09 | Simplify vfncvt | eopXD | 1 | -0/+70 | |
2021-12-07 | Merge pull request #879 from eopXD/simply-insts | Andrew Waterman | 1 | -42/+124 | |
Simply floating point parameters and merge operations | |||||
2021-12-07 | Simplify vadc and vsbc (#876) | Yueh-Ting (eop) Chen | 1 | -6/+10 | |
2021-12-07 | Merge pull request #868 from eopXD/simplify-narrowing-inst | Andrew Waterman | 1 | -47/+54 | |
Simplify narrowing instruction | |||||
2021-12-08 | Simplify vmerge, vfmerge | eopXD | 1 | -5/+66 | |
2021-12-08 | Simplify floating point compare instructions | eopXD | 1 | -13/+35 | |